Browsing by Author "Shih, YH"

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A dual mode channel decoder for 3GPP2 mobile wireless communications
(2004)
Lin, CC
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Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52Mb/s and 5.26Mb/s data rates respectively The memory access is reduced by the input caching scheme. And the system complexion is lowered by the efficient interleaver design. This chip is fabricated in a 0.18mum six-metal standard CMOS process, and the measured power dissipation is 83mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.
A low power turbo/Viterbi decoder for 3GPP2 applications
(2006-04-01)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-mu m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.
A novel fixed bit plane error resilient image coding for wireless multimedia transmission
(2002)
Wei, HK
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Lee, YS
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Shih, YH
;
Lee, CY
;
電子工程學系及電子研究所
Variable length code (VLC) is the most popular technique using for DCT-based [1] image compression standards such as JPEG MPEG and H.26x. Unfortunately it is highly sensitive to the channel noise. For wireless multimedia transmission, any error bit will cause serious error propagation and result in large image quality degradation. Moreover, it usually has no retransmission chance for real time applications. As a result, high error resilient image coding scheme is important for wireless applications. We propose a novel DCT-based fixed bit plane error resilient image coding (FBP-ERIC) scheme, which can minimize error propagation effect with low redundancy. The complexity is much less than conventional coding schemes In addition, it has high accurate error detection capability for performing error concealment. Even at 0.1% bit-error-rate, 46.5% of erroneous blocks can be accurately detected. Hence, high image quality (PSNR=32.06dB) can be obtained by applying simple error compensation mechanism.
Design of a power-reduction viterbi decoder for WLAN applications
(2005-06-01)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-mu m standard CMOS process. The test results show that 30 similar to 40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.