Browsing by Author "Shih, Yen-Hao"

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A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance
(2015)
Lo, Roger
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Du, Pei-Ying
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Hsu, Tzu-Hsuan
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Wu, Chen-Jun
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Guo, Jung-Yi
Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.
Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices
(2014-06-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chang, Kuo-Pin
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Shih, Yen-Hao
The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.
Modeling the Variability Caused by Random Grain Boundary and Trap-location Induced Asymmetrical Read Behavior for a Tight-pitch Vertical Gate 3D NAND Flash Memory Using Double-Gate Thin-Film Transistor (TFT) Device
(2012-01-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chen, Chih-Ping
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Chang, Kuo-Ping
The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.
Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs
(2010)
Lai, Erh-Kun
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Chien, Wei-Chih
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Chen, Yi-Chou
;
Hong, Tian-Jue
;
Lin, Yu-Yu
A complementary metal oxide semiconductor (CMOS)-compatible WO(x) based resistive memory has been developed. The WO(x) memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast (similar to 2 ns) and the programming voltage (< 1: 4 V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and 10(8)-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO(x) resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications. (C) 2010 The Japan Society of Applied Physics