Browsing by Author "Shih, Yi-Hsin"

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An 81.6 mu W FastICA Processor for Epileptic Seizure Detection
(2015-02-01)
Yang, Chia-Hsiang
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Shih, Yi-Hsin
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Chiueh, Herming
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電機資訊學士班
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電子工程學系及電子研究所
To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 mm(2). The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 mu W at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 x computation speedup are achieved. The performance of the chip was verified by human dataset.
Hardware-Efficient EVD Processor Architecture in FastICA for Epileptic Seizure Detection
(2012)
Shih, Yi-Hsin
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Chen, Tsan-Jieh
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Yang, Chia-Hsiang
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Chiueh, Herming
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交大名義發表
Independent component analysis (ICA) is a key signal processing technique to improve the detection accuracy of epileptic seizures. It separate artifacts and epileptic signals, which facilitates the succeeding signal processing for seizure detection. FastICA is an efficient algorithm to compute ICA through proper pre-processing. In the preprocessing stage of the FastICA, eigenvalue decomposition (EVD) is applied to reduce the convergence time of iterative calculation of weights for demultiplexing received multi-channel signals. To calculate EVD efficiently, the Jacobi method is preferable since an array structure is proposed to decompose matrix efficiently by leveraging givens rotations. Multiple diagonal and off-diagonal processing elements run in parallel to calculate EVD. The micro-rotations can be realized efficiently by coordinate rotation digital computer (CORDIC), which calculates trigonometric functions using only addition, shift, and table lookup without dedicated multipliers. In this work, an approximate Jacobi method is adopted instead to reduce the number of iterations significantly. Optimized rotation angles can be calculated efficiently using shift-add operations for multiplications with coefficients of power of 2 in the diagonal processing elements. Normalization operation in the original mathematical formulation can be omitted due to signal re-scaling in both diagonal and off-diagonal processing elements. The number of processing cycles is reduced by 6 times for each sweep due to the reduced number of pipelining stages in the critical path. The approximate Jacobi method provides a 6x speedup (185-252 cycles instead of 1440 cycles) for a 6-channel EVD. An overall 77.2% area reduction is achieved due to arithmetic simplification and hardware reduction. The hardware architecture is verified by testing the human electroencephalogram (EEG) signals from the Freiburg Seizure Prediction EEG (FSPEEG) database.