Browsing by Author "Shih Wei-Chiang"

Now showing 1 - 12 of 12

Data-aware dynamic supply random access memory
(2013-01-01)
Chuang Ching-Te
;
Yang Hao-I
;
Lin Yi-Wei
;
Hwang Wei
;
Shih Wei-Chiang
A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY
(2012-02-23)
Chuang Ching-Te
;
Yang Hao-I
;
Lin Yi-Wei
;
Hwang Wei
;
Shih Wei-Chiang
A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
LOW POWER STATIC RANDOM ACCESS MEMORY
(2012-01-12)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Hwang Wei
;
Chen Chia-Cheng
A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.
Low power static random access memory
(2014-02-25)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Hwang Wei
;
Chen Chia-Cheng
A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.
Oscillato based on a 6T SRAM for measuring the bias temperature instability
(2014-08-12)
Chuang Ching-Te
;
Jou Shyh-Jye
;
Hwang Wei
;
Tsai Ming-Chien
;
Lin Yi-Wei
The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.
Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability
(2013-08-29)
Chuang Ching-Te
;
Jou Shyh-Jye
;
Hwang Wei
;
Tsai Ming-Chien
;
Lin Yi-Wei
The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.
SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
(2013-08-29)
CHUANG Ching-Te
;
Jou Shyh-Jye
;
Hwang Wei
;
Lin Yi-Wei
;
Tsai Ming-Chien
The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.
Static random access memory with data controlled power supply
(2012-11-27)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Lin Yung-Wei
;
Lu Chien-Yu
A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY
(2012-01-12)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Lin Yung-Wei
;
Lu Chien-Yu
A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
Threshold voltage measurement device
(2013-11-12)
Chuang Ching-Te
;
Jou Shyh-Jye
;
Lin Geng-Cing
;
Wang Shao-Cheng
;
Lin Yi-Wei
A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.
VARIATION-TOLERANT WORD-LINE UNDER-DRIVE SCHEME FOR RANDOM ACCESS MEMORY
(2012-02-09)
Chuang Ching-Te
;
Lin Yi-Wei
;
Chen Chia-Cheng
;
Shih Wei-Chiang
A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.
Variation-tolerant word-line under-drive scheme for random access memory
(2012-07-03)
Chuang Ching-Te
;
Lin Yi-Wei
;
Chen Chia-Cheng
;
Shih Wei-Chiang
A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.