Browsing by Author "Shiu, RM"

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Aggressive scheduling for memory accesses of CISC superscalar microprocessors
(2001-09-01)
Shiu, RM
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Hwang, HY
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Shann, JJJ
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資訊工程學系
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Department of Computer Science
For CISC microprocessors, the proportion of memory access instructions is relatively high, and a specific address is likely to be accessed repeatedly in a short period of time because of register-to-memory or memory-to-memory instruction set architectures and limited register sets. As superscalar architectures advance, an aggressive scheduling policy for memory access becomes crucial. In this paper, we examine the scheduling policies of loads/stores on CISC superscalar processors and develop an aggressive scheduling policy called preload. The preload scheduling policy allows loads to precede the earlier unsolved pending stores, and delays the checking of conflict and forwarding of data until the data is loaded, thereby allowing greater tolerance of the latency for address generation. Because of its popularity, we focus our attention on the x86 instruction set. Simulation results show that the preload achieves a higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the preload can achieve even higher performance.
An X86 load/store unit with aggressive scheduling of load/store operations
(1998)
Hwang, HY
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Shiu, RM
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Shann, JJJ
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資訊工程學系
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Department of Computer Science
Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive scheduling policy of load/store operations becomes crucial. In this paper, we examine the scheduling policies of loads/stores on x86 superscalar microprocessors and propose a new aggressive scheduling policy called load speculation, which allows loads to precede the previous unsolved pending stores. Simulation results show that the load speculation achieves the higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the load speculation can achieve even higher performance.
Applying stack simulation for branch target buffers
(2000-05-15)
Shiu, RM
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Lu, NP
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Chung, CP
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資訊科學與工程研究所
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Institute of Computer Science and Engineering
Branch target buffer (BTB) is widely used in modern microprocessor designs to reduce the penalties caused by branches. To evaluate the performance of a BTB, trace-driven simulation is often used. However, as the trace of a typical program is very large, the simulation time is often too long. To reduce the simulation time, we developed a stack simulation technique for BTB to evaluate many sets of design parameters in one simulation pass. Due to the fact that the prediction information in the BTB does not have the inclusion property - a property which makes the stack simulation work, we propose a state vector method to enumerate the prediction information for different sets of BTB design parameters to mimic the inclusion property. Simulation results show that the state vector method greatly reduces the simulation time. The speedup of the stack simulation for BTB proposed in this paper over the traditional BTB simulation is 4.68 in terms of simulation time when 13 sets of BTB design parameters are simulated in one simulation pass. (C) 2000 Elsevier Science Inc. All rights reserved.
Decoding of CISC instructions in superscalar processors with high issue rate
(2000-03-01)
Shiu, RM
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Chiu, JC
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Cheng, SK
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Shann, JJJ
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資訊工程學系
The paper examines the design issues of decoders, including the primitive operation (POP) translation strategies and the decoding rules, for CISC superscalar processors to exploit a higher degree of parallel execution. Attention is focused on the x 86 instruction set because of its popularity. There are two different approaches regarding POP translation strategies: one is to merge the address generation into load/store operations, and the other is to translate the isolated address generation operations. Simulation results show that, in high issue-rate decoders, the latter strategy improves the performance by 20 to 25 %. Furthermore, considering the tradeoffs between the hardware cost and performance, a cost-effective decoding rule suitable for current commercial programs is recommended.
Decoding unit with high issue rate for X86 superscalar microprocessors
(1998)
Cheng, SK
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Shiu, RM
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Shann, JJJ
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資訊工程學系
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Department of Computer Science
In the new generation of x86 microprocessors, superscalar techniques are used to achieve higher performance by executing multiple instructions in parallel. For compatibility and higher execution parallelism, the decoding units of these microprocessors translate the x86 instructions into primitive operations. These microprocessors translate x86 instructions by the similar rca? of merging address generating into load/store operations. In this paper, we develop a nerv translating strategy of translating isolated address generation operations. Simulation results show that, in high issue rate decoding units, translating isolated address generation operations improves the performance for 20% to 25%. Besides, we find that enhancing the store buffer with the ability of snooping result buses is important for high issue rate decoding units. Furthermore, considering the tradeoff of the hardware cast and performance, we examine the decoding rules to design a decoding unit. According to the simulation results,,ve suggest a good decoding rule suitable for current commercial programs.
Instruction cache prefetching directed by branch prediction
(1999-09-01)
Chiu, JC
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Shiu, RM
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Chi, SA
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Chung, CP
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資訊科學與工程研究所
As the gap between processor speed and memory speed grow, so the performance penalty of instruction cache misses gets higher. Instruction cache prefetching is a technique to reduce this penalty. The prefetching methods determine the target line to be prefetched generally based on the current fetched line address. However, as the cache line becomes wider, it may contain multiple branches. This is a hurdle which must be overcome. The authors have developed a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches, called branch instruction based (BIB) prefetching; in which the prefetch information is recorded in an extended BTB. Simulation results show that for commercial benchmarks, BIB prefetching outperforms traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average. As BTB designs become more sophisticated and achieve higher hit and accuracy ratios, BIB prefetching can achieve a higher level of performance.
Instruction cache prefetching with extended BTB
(1997)
Chi, SA
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Shiu, RM
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Chiu, JC
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Chang, SE
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Chung, CP
Instruction cache prefetching is a technique to reduce the penalty caused by instruction cache misses. The prefetching methods generally determines the target fine to be prefetched based on the current fetched fine address. However, as the cache fine becomes wider, there may be multiple branches in a cache fine which hurdles the decision made by these methods. This paper develops a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches. We call it the branch instruction based (BIB) prefetching, In BIB prefetching, the prefetch information is recorded in an extended BTB. Simulation results show that, the BIB prefetching outperforms the traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average, iis the BTB designs become more sophisticated and achieve higher hit and accuracy ratio the BIB prefetching can achieve higher performance.
Register renaming for x86 superscalar design
(1996)
Liu, CC
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Shiu, RM
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Chung, CP
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資訊科學與工程研究所
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Institute of Computer Science and Engineering