Browsing by Author "Shiue, Muh-Tian"

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10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop
(2009)
Lin, Yu-Chun
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Shiue, Muh-Tian
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Decision feedback equalizer (DFE) uses a feedback path to cancel post-cursor IS!, and this feedback path will also cause the limitation of its maximum throughput rate. This paper proposes a new lookahead method to break the feedback path for multi-gigabit DFE design. After lookahead computation, each paralleled sub-circuit has the same throughput rate as original one. Therefore, the total throughput rate is proportional to the parallelization factor. The computation complexity of the proposed architecture is lower than that of multiplexer-based lookahead DFE if the tap number of the feedback filter is large. It is shown that the new method saves 10% hardware complexity for an 8 taps feedback filter DFE and 98% hardware complexity for a 12 taps feedback filter DFE in comparison to a 10Gbps multiplexer-based lookahead DFE.
A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization
(2008)
Wei, Ting-Chen
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Liu, Wei-Chang
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Tseng, Chi-Yao
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Long, Syu-Siang
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Jou, Shyh-Jye
An OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and +/- 50 subcarrier spacing carrier frequency offset (CFO) in multipath environment The total memory requirement of this chip is 102.8KB and the total equivalent gate count (including memory) is about 806,800 gates. By using 0.18 mu m CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600 mu m x 3600 mu m.
Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2(k))
(2015-04-01)
Wey, Chin-Long
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Jui, Ping-Chang
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Shiue, Muh-Tian
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2(k)) operation with additions. No multiplications are needed. The value of (1+2(k))N can be computed by adding N to its k-bit left-shifted value 2(k)N. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.
Low-Cost Parallel FFT Processors with Conflict-Free ROM-Based Twiddle Factor Generator for DVB-T2 Applications1
(2013)
Jui, Ping-Chang
;
Wey, Chin-Long
;
Shiue, Muh-Tian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a conflict-free ROM addressing scheme for generating the TF tables. Basically, the conventional (N/2)-words ROM table for the Radix-2 Memory-Based FFT (MBFFT) processor with single process element (PE) is equally partitioned into 2(p) sub-tables allowing all 2(p) PEs to simultaneously access the twiddle factors without causing any conflict. This study presents the use of MBFFT processor with 4 parallel PEs. Result show that the proposed scheme can reduce the chip area of DVB-T2 applications by 18.85%. The hardware reduction is of significance.
Multiplication of a Constant (2(k) +/- 1) and Its Fast Hardware Implementation
(2016-01-01)
Jui, Pin-Chang
;
Wey, Chin-Long
;
Shiue, Muh-Tian
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
Constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units and they are prevalent in modern VLSI designs. This study presents efficient algorithms and their fast hardware implementation for performing multiplying-by-(2(k) +/- 1), or (2(k) +/- 1)N, operation with additions. No multiplications are needed. The value of (2(k) +/- 1)N can be computed by adding (+/- N) to its k-bits left-shifted value 2(k)N. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper presents the unit cells for additions (UCAs). Results show that the UCA-based RCA achieves 34 % faster than the FA-based RCA. Further, in order to improve the speed performance with lower hardware cost, this paper also presents a simple and modular hybrid adder with the proposed UCA concept, where the hybrid adder takes the lower-bit carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the proposed hybrid adder achieved speed performance improvement while maintaining its modular and regular structure.