Browsing by Author "Shrestha, Niraj Man"

Now showing 1 - 7 of 7

A novel AlGaN/GaN multiple aperture vertical high electron mobility transistor with silicon oxide current blocking layer
(2015-08-01)
Shrestha, Niraj Man
;
Wang, Yuen Yee
;
Li, Yiming
;
Chang, Edward Yi
;
材料科學與工程學系
In this work, a new AlGaN/GaN vertical high electron mobility transistor (HEMT) with silicon oxide (SiO2) current blocking layer (CBL) is designed and studied numerically for high-power devices. To overcome the excessive vertical leakage through CBL layer in conventional p-GaN CBL vertical HEMT, large band-gap material, SiO2 is, for the first time, introduced as a CBL material. The band-gap of SiO2 leads to a large barrier which can effectively suppress the vertical leakage even at high drain bias and enhance the breakdown voltage to 1270 V (154% enhancement compared with the conventional p-GaN CBL vertical HEMT). In addition, a device with four parallel apertures is proposed to reduce the aperture resistance, where the total aperture thickness is equal to the aperture thickness of the conventional one. Therefore, the drain current is increased. We not only focus on the vertical leakage control, but also, on the drain current boost (7% improvement). (c) 2014 Elsevier Ltd. All rights reserved.
Design and Simulation of High Performance Lattice Matched Double Barrier Normally Off AlInGaN/GaN HEMTs
(2020-01-01)
Shrestha, Niraj Man
;
Li, Yiming
;
Chen, Chao-Hsuan
;
Sanyal, Indraneel
;
Tarng, Jenn-Hawn
A novel lattice matched double barrier Al0.72In0.16Ga0.12N/Al0.18In0.04Ga0.78N/GaN normally-off high electron mobility transistor (HEMT) is designed and simulated by solving a set of thermodynamic transport equations. Using the experimentally calibrated physical models with bearing mobility degradation by surface roughness in account, the recess gate and double barrier of the proposed device achieves a maximum drain current density (I-D,I-max) of 1149 mA/mm and a maximum transconductance (g(m,max)) of 358 mS/mm with a positive threshold voltage (Vth) of 0.2 V. The small polarization charge of first barrier is responsible for positive Vth. I-DS,I-max in the double barrier HEMT at high gate bias condition is due to injection of electrons from upper 2DEG which is almost impossible at lower gate voltage because of insufficient energy to cross the barrier. The injection of electrons is further supported by the second peak in the g(m) curve at low gate bias V-G = 1V. The outcome of this study suggests that the proposed device will be beneficial for high-frequency and high-power electronic applications.
Device Simulation of P-InAlN-Gate AlGaN/GaN High Electron Mobility Transistor
(2014-01-01)
Shrestha, Niraj Man
;
Lin, Yueh-Chin
;
Chang, Han-Tung
;
Li, Yiming
;
Chang, Edward Yi
Enhancement mode AlGaN/GaN high electron mobility transistor with p-InAlN gate is designed and successfully studied its electrical properties. Threshold voltage of the device is 1.9 V, which is required magnitude of threshold voltage for real device. Similarly, the maximum drain current is 520 mA/mm and trasconductance is 183 mS/mm, which is the record estimation for enhancement-mode (e-mode) device with recorded threshold voltage. P-InAlN layer injects hole to the barrier at higher gate voltage and results in comparatively larger drain current. Selective area etching and re-grow AlInN causes thin barrier layer beneath the gate. This recess like p-InAlN structure can reduce the concentration of 2DEG; and thus results the high magnitude of threshold voltage.
Electrical Characteristic of AlGaN/GaN High-Electron-Mobility Transistors With Recess Gate Structure
(2019-04-01)
Shrestha, Niraj Man
;
Li, Yiming
;
Suemitsu, Tetsuya
;
Samukawa, Seiji
;
交大名義發表
AlGaN/GaN high-electron-mobility transistors (HEMTs) with nonrecess and recess gates are simulated by solving a set of drift-diffusion equations for electrostatic potential and electron-hole concentrations with self-heating model. The approach is first calibrated for both HEMT devices with experimentally measured data, to provide the best accuracy of the simulation. Recess gate device suffers from high potential to the channel, increased parasitic resistances, and deep level traps in barrier due to surface roughness. In addition, selective thinning of the barrier and increase parasitic resistance results in 17% reduction on the carrier concentration. The carrier mobility degradation due to surface roughness and electron velocity lessen due to high electric field result shrinkage of current density with considerable shift of the threshold voltage toward positive value. Even though transconductance does not seems to be remarkably changed for 3-nm recess gate, its value increases on deeper recess. This paper reveals that surface roughness is crucial issue that has dominant role behind the low current density in the recess gate structure. The detail physical understanding of the recess technology will be helpful to minimize the performance deterioration of the explored devices.
Low resistive InGaN film grown by metalorganic chemical vapor deposition
(2020-01-01)
Shrestha, Niraj Man
;
Chauhan, Prerna
;
Wong, Yuen-Yee
;
Li, Yiming
;
Samukawa, Seiji
Indium gallium nitride (InGaN) samples were grown on sapphire substrate with low temperature GaN buffer by metalorganic chemical vapor deposition (MOCVD) under varying growth conditions, such as temperature, pressure and ammonia flow. Although high indium composition is considered as indispensable parameter for sheet carrier concentration (n(s)) and low sheet resistance (R-s), our outcomes disclose that higher indium composition in InGaN film doesn't always have high n(s) and low R-s. Acceptor nature of carbon related defects, a major trapping sites for electrons, plays a crucial role to limit the carrier concentrations in the InGaN specially grown at low pressure, low temperature and low ammonia flow. Furthermore, study of metal contacts deposited on the grown samples by transmission line method (TLM) shows that carrier concentration is the most important factor to obtain low contact resistance. The measured contact resistance for the sample with 4.5x 10(16) cm(2) carrier concentration is 0.13 Omm which is among the lowest contact resistance for GaN based materials grown by MOCVD. This proves that the use of InGaN in source and drain contact region can surpassingly reduce contact resistance and significantly improve device performance of AlGaN/GaN device.
Optimal design of the multiple-apertures-GaN-based vertical HEMTs with SiO2 current blocking layer
(2016-03)
Shrestha, Niraj Man
;
Li, Yiming
;
Chang, Edward Yi
;
材料科學與工程學系
;
資訊工程學系
Gallium nitride (GaN) based vertical high electron mobility transistor (HEMT) is very crucial for high power applications. Combination of advantageous material properties of GaN for high speed applications and novel vertical structure makes this device very beneficial for high power application. To improve the device performance especially in high drain bias condition, a novel GaN based vertical HEMT with silicon dioxide (SiO2) current blocking layer (CBL) was reported recently. In this paper, effects of the thickness of CBL layer and the aperture length on the electrical and breakdown characteristics of GaN vertical HEMTs with SiO2 CBL are simulated by using two-dimensional quantum-mechanically corrected device simulation. Intensive numerical study on the device enables us to optimize and conclude that devices with 0.5-mu m-thick SiO2 layer and 1-mu m-long aperture will be beneficial considerations to improve the device performance. Notably, using the multiple apertures can effectively reduce the on-state conducting resistance of the device. On increasing the number of apertures, the drain current is increased but the breakdown voltage is decreased. Therefore, device with four apertures is taken as an optimized result. The maximum drain current of 84 mA at V-G = 1V and V-D = 30 V, and the breakdown voltage of 480 V have been achieved for the optimized device.
Simulation study on electrical characteristic of AlGaN/GaN high electron mobility transistors with AlN spacer layer
(2014-04-01)
Shrestha, Niraj Man
;
Li, Yiming
;
Chang, Edward Yi
;
材料科學與工程學系
;
資訊工程學系
Two-dimensional electron gas (2DEG) property is crucial for the performance of GaN-based high electron mobility transistors (HEMTs). The 2DEG-related concentration and mobility can be improved as device\'s performance booster. Electrical characteristics of AlGaN/AlN/GaN HEMT are numerically simulated and compared with conventional AlGaN/GaN HEMT. The main findings of this study indicate that 2DEG\'s concentration level is increased when a spacer layer of AlN in the interface of AlGaN/AlN/GaN is inserted owing to large conduction band off set, high polarization field, and high barrier. Notably, when a thin spacer layer of AlN is introduced, the 2DEG\'s distribution virtually shifts away from the interface which reduces the interface scattering. The scattering appearing in conventional AlGaN/GaN HEMT includes alloy and interface roughness scatterings. They are reduced in AlGaN/AlN/GaN HEMT due to binary nature of AlN material. A critical thickness of spacer layer for mobility is 0.5nm and the maximum drain current and transconductance (G(m)) are at 1.5 and 1.2nm thickness of AlN spacer layer. Increasing thickness of AlN spacer layer deteriorates the ohmic resistance of source/drain contact and hence degrades the performance of device beyond 1.5-nm-thick AlN spacer layer. (C) 2014 The Japan Society of Applied Physics