Browsing by Author "Shung, CB"

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A (208,192;8) Reed-Solomon decoder for DVD application
(1998)
Chang, HC
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The Digital Versatile Disk (DVD) is an emerging standard to meet the ever increasing storage capacity requirement of future high quality video and audio applications. In this paper, we implement a (208, 192; 8) Reed-Solomon decoder for the DVD Reed-Solomon product code (RS-PC). We propose a new area-efficient architecture which uses only three finite field multipliers (FFMs) to implement the inversion-less Berlekamp-Massey algorithm. The error value evaluator employs an algorithm-based GF(2(m)) inverter instead of an inversion ROM-table. We implement the (208, 192; 8) Reed-Solomon decoder using a 0.6 mu m SPDM CMOS technology with an area of 12.35 mm(2) (core area 6.45 mm(2)). The chip can run at 16.67MHz, while the DVD requirement is 3.74MHz. A minor error was found in this first version which a corrected in the second version of the chip.
A combined channel assignment mechanism for hierarchical cellular systems
(1998-09-01)
Lo, KR
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Chang, CJ
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Chang, C
;
Shung, CB
;
電子工程學系及電子研究所
This paper proposes a combined channel assignment (CCA) mechanism for hierarchical cellular systems with overlaying macrocells and overlaid microcells. The proposed CCA mechanism combines overflow, underflow, and reversible schemes, where new or handoff calls having no available channel to use in the overlaid microcell can overflow to use free channels in the overlaying macrocell, handoff calls from a neighboring macrocell can underflow to use free channels in the overlaid microcell, and handoff attempts from a macrocell-only region to an overlaid microcell can be reversed to use free channels in the microcell. We apply the CCA mechanism in two different hierarchical cellular systems of Strip type and Manhattan type and compare the CCA with the overflow channel assignment (OCA) scheme. Simulation results show that the CCA mechanism outperforms the OCA scheme by once in forced termination probability, by several times in new call blocking probability, and by 4.7% in system utilization for a hierarchical cellular system, and the CCA mechanism is more suitable for the Manhattan type than for the Strip type. (C) 1998 Elsevier Science B.V.
A neural fuzzy resource manager for hierarchical cellular systems supporting multimedia services
(2003-09-01)
Lo, KR
;
Chang, CJ
;
Shung, CB
;
交大名義發表
;
National Chiao Tung University
Using intelligent techniques to perform radio resource management is an effective method. This paper proposes neural fuzzy control for radio resource management in hierarchical cellular systems supporting multimedia services. A neural fuzzy resource manager (NFRM) is designed, which mainly contains a neural fuzzy channel allocation processor (NFCAP), and NFCAP is in a two-layer architecture: a fuzzy cell selector (FCS) in the first layer and a neural fuzzy call-admission and rate controller (NFCRC) in the second layer. The FCS chooses not only the handoff failure. probabilities and the resource availabilities in both microcell and macrocell but also the mobility of user as input linguistic variables. The NFCRC takes the handoff failure probability and the resource availability of the selected cell as input variables to perform call admission control and rate control for the call. Simulation results show that NFRM can always gruarantee the quality of service (QoS) requirement of handoff failure probability for all traffic loads. Also, NFRM improves the system. utilization by 31.1% while increasing the handoff rate by 2% over the overflow channel allocation (OCA) scheme [3]; it enhances the system utilization by 6.3% and 1.4%, and still reduces the handoff rate by 14.9% and 6.8%, as compared to the combined channel allocation (CCA) scheme [201, [21] and fuzzy channel allocation control (FCAC) scheme [9], respectively, under a predefined QoS constraint.
A QoS-guaranteed fuzzy channel allocation controller for hierarchical cellular systems
(2000-09-01)
Lo, KR
;
Chang, CJ
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Chang, C
;
Shung, CB
;
電信工程研究所
This paper proposes a fuzzy channel allocation controller (FCAC) for hierarchical cellular systems. The FCAC mainly contains a fuzzy channel allocation processor (FCAP) which is designed to be in a two-layer architecture that consists of a fuzzy admission threshold estimator in the first layer and a fuzzy channel allocator in the second layer. The FCAP chooses the handoff failure probability, defined as quality-of-service (QoS) index, and the resource availability as input linguistic variables for the fuzzy admission threshold estimator, where the Sugeno's position gradient-type reasoning method is applied to adaptively adjust the admission threshold for the fuzzy channel allocator. And the FCAP takes the mobility of user, the channel utilization, and the resource availability as input variables for the fuzzy channel allocator so that the channel allocation is finally determined, further based upon the admission threshold. Simulation results show that FCAC can always guarantee the QoS requirement of handoff failure probability for all traffic loads, Also it improves the system utilization by 31.2% while it increases the handoff rate by 12.9% over the overflow channel allocation (OCA) scheme [7]; it enhances the system utilization by 6% and still reduces the handoff rate by 6.7% as compared to the combined channel allocation (CCA) scheme [10], under a defined QoS constraint.
A queue manager chip for shared buffer ATM switches
(1996-11-01)
Lin, YS
;
Huang, HC
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an efficient queue manager chip for controlling a 16 x 16 shared buffer ATM switch with a 256-cell buffer. Compared to conventional implementations of queue managers for shared buffer ATM switches, our design eliminates the idle address FIFO and the pre-allocated bubbles at the tails of output queues. The former reduces the storage size required for queue management, while the latter improves the effective buffer capacity. Such modular implementation also provides flexibilities in queue management implementation. Backpressure with soft-full and hard-full flow control for multi-stage expansion and two priority classes with push-out cell discarding are supported without extra hardware overhead. This chip was designed and fabricated using 0.8 mu m CMOS technology. It has 35,700 transistors in a chip area of 28.3 mm(2), with a core of 10.4 mm(2) and 31,960 transistors. Two test sequences were developed during the design phase to fully verify the queue management functions of the prototype chip. The queue manager chip was tested up to 36 MHz, and is able to control a 16 x 16 shared buffer switch with a 155 MHz link rate.
A queue manager chip for shared buffer ATM switches
(1996-11-01)
Lin, YS
;
Huang, HC
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an efficient queue manager chip for controlling a 16 x 16 shared buffer ATM switch with a 256-cell buffer. Compared to conventional implementations of queue managers for shared buffer ATM switches, our design eliminates the idle address FIFO and the pre-allocated bubbles at the tails of output queues. The former reduces the storage size required for queue management, while the latter improves the effective buffer capacity. Such modular implementation also provides flexibilities in queue management implementation. Backpressure with soft-full and hard-full flow control for multi-stage expansion and two priority classes with push-out cell discarding are supported without extra hardware overhead. This chip was designed and fabricated using 0.8 mu m CMOS technology. It has 35,700 transistors in a chip area of 28.3 mm(2), with a core of 10.4 mm(2) and 31,960 transistors. Two test sequences were developed during the design phase to fully verify the queue management functions of the prototype chip. The queue manager chip was tested up to 36 MHz, and is able to control a 16 x 16 shared buffer switch with a 155 MHz link rate.
A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications
(2001-02-01)
Chang, HC
;
Shung, CB
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a Reed-Solomon Product-Code (RS PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder, The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm. The proposed RS-PC decoder solution was implemented using 0.6-mum CMOS single-poly double-metal (SPDM) standard cells. The chip size is 4.22 x 3.64 mm(2) with a core area of 2.90 x 2.88 mm(2),where the total gate count is about 26K, Test results show that the proposed RS-PC decoder chip can support 4x DVD speed with off-chip frame buffers or 8x DVD speed with embedded frame buffers operating at 3 V.
Accurate logic-level power simulation using glitch filtering and estimation
(1996)
Tsai, WC
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Shung, CB
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Wang, DC
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交大名義發表
;
電子工程學系及電子研究所
Power estimation tool is needed to be more fast and accurate when the power consumption is the chief concern during the chip design. Logic-level simulator is a good choice to estimate the power consumption of a chip design. In this paper we attempt to improve the accuracy of a logic-level simulator using glitch filtering and estimation techniques. We use logic-level simulator to filter some glitches and estimate the glitch power. We use slope of transition and time interval of two consecutive transitions to decide whether these transitions is partial glitches or full transitions. We estimate the transition power of each transition event and summed them up. The power simulation error is reduced from 35.8% to 7.9% referring to the Spice simulation.
An efficient architecture for multicasting in shared buffer ATM switches
(1998-02-01)
Lin, YS
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Multicast ATM switches are essential to support various types of services in the Broadband ISDN. In this paper we present an efficient architecture to support multicasting in shared buffer ATM switcher. A lookahead technique is employed to resolve the head-of-line blocking problem in the multicast-queue approach, thus improving the throughput of the multicast traffic. The arbitration between multicast and unicast services is investigated to prevent the lookahead technique from increasing the multicast dominance. We show through performance and complexity comparisons that with a small hardware overhead over the multicast-queue approach, our architecture provides a throughput performance comparable to address-duplication or searchable-queue-based approaches.
Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs
(2000-12-01)
Chuang, HH
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Jou, JY
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Shung, CB
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired nonhomogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of nun-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates Favorable results for Xilinx XC4000 CLBs, Over a set of MCNC benchmarks. our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.
Design of knockout concentrators
(1998-06-01)
Lin, YS
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Shung, CB
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Chen, JC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The knockout switch architecture has been found attractive for large-scale switch implementations because of its satisfactory cell loss performance, with constant output buffer speed-up independent of switch dimension. The per port hardware complexity of a knockout concentrator, however, does grow linearly with the switch dimension. In the paper, several approaches are investigated to reduce the complexity of the knockout while retaining the cell loss performance. A bufferless hierarchical concentrator architecture with reduced hardware complexity is derived. The concentrator complexity can be further reduced by introducing buffers in the concentrator, and the trade-off is analysed. Furthermore, output grouping may be applied in the buffered hierarchical concentrator to reduce the per port complexity. Two large-scale switch design examples are derived using the proposed design approaches, producing a complexity reduction ranging from 1.2% to 89.7%.
Event-driven power estimation of CMOS circuits
(1997-10-01)
Tsai, WC
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Fast and accurate power estimation has become an important topic with the increasing need for low power electronics. In this paper we address the problem of using event-driven simulation tools for power estimation. We identify and compare two approaches: input-driven and output-driven, and propose several ways of improvement. The estimation accuracy is degraded in event-driven power estimators due to superfluous and partial glitches. We described glitch filtering and estimation techniques pertaining to input-driven and output-driven power estimators. An output-driven power estimator, Peony, was developed which used the proposed path pouter idea to improve the estimation accuracy. It achieved significant power estimation accuracy improvement at a speed of two orders of magnitude faster than Spice.
Multiple-training bi-directional adaptive equalizers for TDMA digital cellular systems
(1996-07-01)
Chen, MJ
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Shung, CB
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, two popular adaptive equalization methods, fractionally spaced decision feedback equalization (FSDFE) and maximum-likelihood sequence estimation (MLSE), are investigated for the design of digital mobile receivers for the IS-54 specifications of the NADC* system. A hi-directional equalization technique is incorporated and a multiple training LMS (MT-LMS) algorithm is used as the adaptive algorithm for both equalization methods. The results show that both MT-MLS and bi-directional techniques are effective in improving the receiver performance. However, the MT-LMS algorithm is more useful for MLSE than FSDFE whereas the bi-directional equalization technique improves FSDFE much more than MLSE.
Multiple-training bi-directional adaptive equalizers for TDMA digital cellular systems
(1996-07-01)
Chen, MJ
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, two popular adaptive equalization methods, fractionally spaced decision feedback equalization (FSDFE) and maximum-likelihood sequence estimation (MLSE), are investigated for the design of digital mobile receivers for the IS-54 specifications of the NADC* system. A hi-directional equalization technique is incorporated and a multiple training LMS (MT-LMS) algorithm is used as the adaptive algorithm for both equalization methods. The results show that both MT-MLS and bi-directional techniques are effective in improving the receiver performance. However, the MT-LMS algorithm is more useful for MLSE than FSDFE whereas the bi-directional equalization technique improves FSDFE much more than MLSE.
New serial architecture for the Berlekamp-Massey algorithm
(1999-04-01)
Chang, HC
;
Shung, CB
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We propose a new efficient serial architecture to implement the Berlekamp-Massey algorithm, which is frequently used in BCH and Reed-Solomon decoders, An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces additional parallelism, We discover a clever scheduling of three finite-field multipliers to implement the algorithm very efficiently, Compared to a previously proposed serial Berlekamp-Massey architecture, our technique significantly reduces the latency.
Queue management for shared buffer and shared multi-buffer ATM switches
(1996)
Lin, YS
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Reactive bandwidth arbitration for priority and multicasting control in ATM switching
(1997)
Fang, SJ
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Lin, YS
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Yang, SC
;
Shung, CB
;
交大名義發表
A new service scheduling scheme, reactive bandwidth arbitration (RBA), is proposed as an effective way to arbitrate the contention among priority classes or between unicast and multicast services in ATM switching. The RBA scheme integrates two previously proposed concepts: bandwidth allocation and reactive arbitration. In, RBA, guaranteed bandwidth is allocated to a connection at call setup based on the traffic characteristics and service requirements, while the arbitration of cell delivery takes into account the queue status to react to traffic fluctuation. Through simulation, we found that by bandwidth allocation, a set of queue threshold levels can be obtained to provide a good approximation to the desired delay performance. Furthermore, around this initial configuration, a linear relationship between the queue threshold and the resulting delay performance car be established to fine-tune the configuration parameters for the desired delay performance. Similar effects were observed as the RBA scheme was applied to arbitrate the contention between unicast and multicast connections in a shared buffer ATM switch. The proposed RBA scheme was incorporated in a queue manager chip for an 8 X 8 shored buffer ATM switch with four priority classes per port and link rate at 622 Mbps. The chip has 130k gates in a chip area of 137.88 mm(2) and operates at 25 MHz.
Special issue on applications of low power design - Preface
(1997-02-01)
Shung, CB
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Yan, RH
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Kubo, M
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Technology mapping for FPGAs with composite logic block architectures
(1996-10-01)
Chuang, HH
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.
Technology mapping for FPGAs with composite logic block architectures
(1996-10-01)
Chuang, HH
;
Shung, CB
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.