Browsing by Author "Song, Hong-Chin"

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A Built-in-Self-Test I sigma-Delta ADC Prototype
(2009-06-01)
Hong, Hao-Chiao
;
Liang, Sheng-Chuan
;
Song, Hong-Chin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a built-in-self-test (BIST) I - pound Delta ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability I - pound Delta modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard -aEuro parts per thousand 6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.
A cost effective BIST second-order Sigma-A-modulator
(2008)
Hong, Hao-Chiao
;
Liang, Sheng-Chuan
;
Song, Hong-Chin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper demonstrates a cost effective built-in-self-test (BIST) E-A modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order E-A modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the con- ventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.