Browsing by Author "Su, Borching"

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A Fully-Integrated Ka-Band 4TX/4RX Phased-Array Transceiver IC in 65nm CMOS
(2016)
Chu, Ching-Yun
;
Tseng, Shao-Ting
;
Gao, Jing-Zhi
;
Chen, Yuan-Pu
;
Chang, Yu-Chen
This paper presents a fully-integrated Ka-band 4RX/4TX phased-array transceiver IC. The four transceiver channels are synchronized by an I/Q standing wave oscillator (SWO). Their signal phases are shifted by hybrid analog IF and LO phase interpolators, and can be controlled digitally and independently. The SWO further composes an on-chip PLL, and is locked to a 1.09 GHz off-chip global reference to scale to a large array at board level. Each receiver channel achieves 66 dB maximum conversion gain and 4.4 dB minimum noise figure. Each transmitter channel achieves 18 dBm maximum output power. The chip is mounted on a high-frequency laminate, inside which embedded cables connect its RF pads to Vivaldi antennas also inside the same PCB. With the PCB, each channel achieves 360 degrees phase shifting capability under a maximum calibrated 3.7 degrees phase errors. The PCB module presents successful beam steering with 23 degrees measured four-channel 3-dB beamwidth. This chip consumes a peak 5 W power at transmit mode, and is fabricated in TSMC 65nm CMOS technology with a 4 x 2.5 mm(2) chip area.
A Ka-Band Scalable Hybrid Phased Array Based on Four-Element ICs
(2020-01-01)
Chu, Ching-Yun
;
Chen, Yuan-Pu
;
Gao, Jing-Zhi
;
Ke, Cheng-Yung
;
Chen, Yu-Wei
In this article, a scalable hybrid phased-array system is presented through synchronization, analog complex weighting, and digital beamforming of numerous fully integrated Ka-band four-receiver (RX)/four-transmitter (TX) phased-array transceiver integrated circuits (ICs). A 1.09-GHz clock synchronizes the local oscillator (LO) and a 50-MHz clock synchronizes analog-to-digital (A/D)/digital-to-analog (D/A) converters for all array elements. Phase shifting is first accomplished in the analog domain using optimal intermediate frequency (IF)/LO complex weighting and signal summing in the 4RX/4TX IC to reduce the number of signals by a factor of four, followed by A/D sampling and digital beamforming in field-programmable gate arrays (FPGAs) and central processing units (CPUs). Phase-shifting properties, programmable gain variations, and antenna patterns of each RTX channel are measured and tabulated to calculate the optimal channel weights. The long-term phase stability is enhanced through temperature control by monitoring all ICs' temperatures in real time and adaptively adjusting the duty cycle of the TX mode of each IC to limit instantaneous temperature variations to +/- 0.5 degrees C over each calibration session. This reduces random phase errors from 13.3 degrees to 4.8 degrees in the TX mode. After each Vivaldi antenna is located on a 2-D rectangular grid, an 8 x 4 subarray module with synchronized digital output is demonstrated. With the boresight pointing along the x-axis, the eight-element dimension pointing along the y-axis, and the four-element dimension pointing along the z-axis, this subarray steers radiation patterns with the E-field polarized to the y-axis between +/- 40 degrees in both azimuth and elevation with 13.4 degrees and 26.4 degrees measured 3-dB beamwidths, respectively.
A Single-Port Duplex RF Front-End for X-Band Single-Antenna FMCW Radar in 65nm CMOS
(2017-01-01)
Kao, Yu-Hsien
;
Chou, Hao-Chung
;
Peng, Chun-Chieh
;
Wang, Yu-Jiu
;
Su, Borching