Browsing by Author "Su, CC"

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A behavior-level fault model for the closed-loop operational amplifier
(2000-09-01)
Chang, YJ
;
Lee, CL
;
Chen, JE
;
Su, CC
;
電子工程學系及電子研究所
In this paper, a simple behavior-level fault model, which is able to represent the faulty behavior of the closed-loop operational amplifier (OP), is presented. The fault model, derived from the macro equivalent circuit of the OP but verified with transistor level simulation, consists of the offset fault and the limited-current fault. It can represent the faulty behavior of the dosed loop OP of all the transistor parametric (soft) faults and many of the catastrophic (hard) faults. Due to its simplicity, the proposed fault model (1) significantly reduces the complexity of fault simulation, and (2) makes closed-form analysis of the faulty behavior of the closed loop OP feasible when the closed loop OP is used as a basic building block of a complicated circuit. Although derived for DC, it can also be applied to AC fault analysis.
A digital LVDS driver with simultaneous switching noise rejection
(2004)
Wang, HW
;
Lu, HW
;
Su, CC
;
電控工程研究所
;
Institute of Electrical and Control Engineering
In this paper, a Digitized LVDS Driver with SSN (Simultaneous switching noise) rejection is proposed, which is fabricated by TSMC 0.18um CMOS technology. First, the power consumption and chip area are greatly decreased due to the design of digitized driver but we suffered the SSN noise. Second, the method which modifies the driver's control signal greatly reduces the ground bounce, and simultaneously solved the ground bound problem mentioned above. Third, the driver can calibrate the output differential mode by the control signal outside the chip by way of the controllable driver. According to the simulation results, ground bounce reduced from 175mV to 95mV, 55% diminished, and the measurement output jitter (pk-pk) is less than 48ps @1.25Gbps. The driver area is only 210um x 210um and power consumption is less than 19mW, which are extremely lower then the conventional LVDS Driver. The proposed programmable driver can also be applied to the 1.5Gbps Serial ATA standard or 2.5Gbps PCI-Express.
A methodology for fault model development for hierarchical linear systems
(2000)
Huang, YC
;
Lee, CL
;
Lin, JW
;
Chen, JE
;
Su, CC
In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers(OP) is demonstrated and presented. The methodology, at first, presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. an application of the derived models to Monte-Carlo simulation to save computation time is also demonstrated.
A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI
(1998)
Lu, CW
;
Lee, CL
;
Chen, JE
;
Su, CC
;
電子工程學系及電子研究所
In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.
A novel LCD driver testing technique using logic test channels
(2003)
Su, CC
;
Wang, WJ
;
Wang, CH
;
Tseng, IS
;
電控工程研究所
This paper proposes a novel voltage measurement technique for LCD driver testing by the use of logic test channel of an ATE. The method is able to achieve less than 1mV error with the presence of 32mV RMS noise.
A spread spectrum clock generator for SATA-II
(2005)
Chen, WT
;
Hsu, JC
;
Lune, HW
;
Su, CC
;
電控工程研究所
In this paper, we proposed a spread spectrum clock generator (SSCG) for the Serial AT Attachment Generation 2 (SATA-II). We use a fractional-N PLL to accomplish the spread spectrum function. The SSCG integrates a conventional PLL, a digital 3(rd) order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 1.5 GHz, a 5000 ppm down spread with a triangular waveform frequency modulation of 33 KHz. The circuit has been simulated in 0.18 um CMOS technology. The non spread spectrum clocking has a jitter of 80 ps and the peak amplitude reduction is 23.44 dBm in spread spectrum mode. The power dissipation from a 1.8 V supply is 55 mW.
A unified approach to detecting crosstalk faults of interconnects in deep submicron VLSI
(2004)
Li, KSM
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
The crosstalk fault effects in deep sub-micron VLSI, namely, glitches and the crosstalk-induced delay, are investigated. The origin of their occurrence, relationship and importance in circuit operation are elucidated. It is shown that the crosstalk-induced delay is only superposition of the induced glitch with the original signal delay on the affected victim line; and crosstalk-induced delay is more important in affecting the circuit performance, and should be considered in more details for testing. A scheme which is to detect both types of faults in a unified way by just detecting glitches is proposed and studied considering the manufacture process variation. In this way, detection of crosstalk-induced faults becomes much easier.
All digital 625Mbps & 2.5Gbps deskew buffer design
(2005)
Lu, HW
;
Chang, YT
;
Su, CC
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper describes an all digital 625Mbps and 2.5Gbps de-skew design for data recovery. It uses a confidence counter to serve as the loop filter that greatly reduces the circuit complexity and improves the jitter compression. The 625Mbps version has been implemented using TSMC 0.18um 1P6M CMOS technology. Measurement results show that the phase resolution is 100ps and the de-skew range is 1.6ns. The output jitter is 48ps and the power consumption is 3.8 mW. For the 2.5Gbps version, the simulation results show that the timing resolution is 26ps, the total de-skew range is 400ps, the output jitter is 26.5ps, and the power consumption is 16 mW.
Analysis of application of the IDDQ technique to the deep sub-micron VLSI testing
(2002-02-01)
Lu, CW
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 x 10(7) gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.
Dynamic analog testing via ATE digital test channels
(2004)
Su, CC
;
Chang, CS
;
Huang, HW
;
Tu, DS
;
Lee, CL
A dynamic analog test methodology using digital tester is proposed. A simple triangular waveform is built on the device interface board for the stimulus generation. The response waveform is quantized by the dual comparators in a digital pin electronic circuit. Statistical analysis is conducted to enhance the quantization resolution and minimize the noise effect. The experimental results using an ATE show that the error is less than 2%. It confirms the feasibility of the proposed methodology.
Fault diagnosis for linear analog circuits
(2001)
Lin, JW
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs "diagnosing evaluators," which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as active faults in OP's.
Fault diagnosis for linear analog circuits
(2000)
Lin, JW
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into discrete signal flow graph, then constructs "diagnosing evaluators", which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power the OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as faults in OP's.
Finite state machine synthesis for at-speed oscillation testability
(2005)
Li, KSM
;
Lee, CL
;
Jiang, T
;
Su, CC
;
Chen, JE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.
Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications
(2005-09-01)
Li, SC
;
Kao, HS
;
Chen, CP
;
Su, CC
;
交大名義發表
A 0.25-mu m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 mu m x 2450 mu m chip area.
Optical recombination-emission characteristics and surface morphologies of InAs quantum dots grown on misoriented GaAs substrate by MOCVD
(2006-03-01)
Hsu, MY
;
Tang, SF
;
Chiang, CD
;
Su, CC
;
Wang, LC
The InAs quantum dot (QD) structures grown on (100) 2 degrees, 6 degrees, 10 degrees, 15 degrees off-angles to (111)A GaAs substrate have been investigated by atomic force microscopy (AFM) and cryogenic photoluminescence (PL). The exact-angle InAs/GaAs is used as the reference sample. The blue shift of PL peak spectra with increasing misoriented scales has also been observed experimentally. In this work, we demonstrated that different off-angle substrates would influence the distribution and uniformity of QD due to variant surface potential energies, which are responsible for the two-stage process (migration and nucleation) of InAs adatoms on the off-angle substrates. (c) 2005 Elsevier B.V All rights reserved.
Windowed multicarrier systems with minimum spectral leakage
(2004)
Lin, YP
;
Jian, YY
;
Su, CC
;
Phoong, SM
;
電控工程研究所
The transmitter output of OFDM or DMT systems with a rectangular window is known to have large spectral side-lobes. Windowing and pulse shaping have been proposed to reduce spectral leakage in the literature. If no extra cyclic prefix is available, windowing at the transmitter requires additional post-processing equalization at the receiver. In this paper we will design optimal windows with minimum spectral leakage. Moreover, we will show that the post processing will affect SNR at the receiver and the resulting SNR can be given in a closed form. Furthermore, we will demonstrate we can have a good trade-off between SNR and spectral leakage.