Browsing by Author "Su, Chung-Cheng"

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A Dual-Input High-Efficiency Li-ion Battery Charger with Current-Mode Smooth Transition and Ripple Reduction Circuits
(2017-01-01)
Su, Chung-Cheng
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Liu, Yen-Wei
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Hung, Chung-Chih
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電機工程學系
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Department of Electrical and Computer Engineering
A Li-ion battery charger with dual input source capability and high efficiency is proposed in this work. An internal source determination circuit could choose the sufficient energy source for charging system. Also, a new approach of smooth transition to avoid oscillation between charging mode switching is used through current-mode-like smooth transition circuit. Pulse frequency modulation with adaptive off-time control is applied to the charger to reduce the requirement of compensation design. The charging current is controlled not only by the current loop but also through the ripple reduction circuit to suppress the increasing charging current ripple as the battery voltage rises. The chip was fabricated in TSMC 0.35-mu m CMOS process.
A ripple-based adaptive on-time controlled buck converter with slope balance technique
(2019-12-01)
Su, Chung-Cheng
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
A ripple-based adaptive on-time controlled buck converter with slope balance technique is presented in this paper. The slope balance technique provides a fixed switching frequency. A 4-bit single-slope analog-to-digital converter (ADC) was used to fix switching frequency when power supply was from 3.3 to 4.5 V. The slope balance technique is proposed to achieve an adaptive on-time control and without extra clock-controlled circuits and current sensing circuits. The input voltage can be predicted from the adaptive on-time by using 4-bit single-slope ADC control. Measurement results show that switching frequency is 1.448 and 1.438 MHz when load current is 200 and 1000 mA, respectively. The proposed buck converter was fabricated in 0.35 mu m CMOS technology with a supply voltage of 4.5 V. The output voltage was measured to be 1.2 V and the load current range was determined to range 200-1000 mA.
An All-Digital Phase-Locked Loop with a Multi-Delay-Switching TDC
(2017-01-01)
Su, Chung-Cheng
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Lin, Cheng-Chung
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Hung, Chung-Chih
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電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a low-power time-to-digital converter (TDC) with multi-delay-switching mechanism for ADPLL application. In order to achieve low power dissipation and low area occupation, a switching mechanism is proposed on TDC design. The proposed ADPLL achieves the frequency range from 150 MHz to 1.45 GHz and 18.4 ps peak-to-peak jitter at 800 MHz. The design has been implemented in 0.18 um CMOS process with an active area of 0.1088 mm(2) and the whole system consumes 8.41 mW at 800 MHz.
Dual active capacitive feedbacks for output capacitor-less low-dropout regulator
(2019-12-01)
Su, Chung-Cheng
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Hung, Chung-Chih
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電機工程學系
;
Department of Electrical and Computer Engineering
An output capacitor-less low-dropout (OCL-LDO) voltage regulator with dual active feedback paths is presented in this paper. The dual active feedbacks provide frequency compensation and spike voltage suppression. Two feedback loops are formed by capacitors C-c and C-a, respectively. The capacitor C-a path detects output voltage to suppress undershoot and overshoot during load transient. The frequency compensation is achieved by capacitor C-c, which helps the LDO regulator not only improve stability, but also enhance transient response without large current consumption. The total utilized capacitance values are only 1.5 pF. The proposed OCL-LDO was fabricated in 0.18 mu m CMOS technology with supply voltage of 1.8 V. The LDO consumes 21 mu A of quiescent current and the chip area is 0.47 mm x 0.49 mm. The measured output voltage difference is 90 mV when the load current is increased from 50 mu A to 100 mA with C-L= 100 pF and recovery time less than 1 mu s. The power supply rejection is - 51.7 dB at 1 kHz.
Dual-output switched-capacitor DC-DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism
(2018-06-01)
Chen, Chia-Min
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Su, Chung-Cheng
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Chou, Fang-Ting
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Hung, Chung-Chih
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電機工程學系
This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC-DC converter was implemented in a standard 0.18-mu m 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively.
Influences of Process Conditions on Stretching Characteristics of Crystalline Polymer Film
(2014-01-01)
Chen, Liang-Yu
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Su, Chung-Cheng
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Chen, Ren-Haw
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機械工程學系
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Department of Mechanical Engineering
Developing the interior structures of polymer films is essential for creating novel functions of such films. This study investigates the effects of extension parameters and processing procedures on the super-structure of a polypropylene (PP) film. An biaxial extension device is also designed and fabricated to analyze the effects of annealing, extension temperature, extension rate and other parameters on the super-structures of PP films. Based on super-structure analyses, the relationships between extension parameters and film structures are determined, and an extension process that involves a second time stretching procedure is suggested. Experimental results indicate that void structures can be generated by biaxial extension at the interface between the crystalline and amorphous regions in a film. The mechanical strength of the film is also affected by stretching and become highly oriented. Although a low extension temperature can increase the number of void structures generated at a low extension ratio, structure sizes are dispersed. Additionally, voids with uniform size can be obtained when the film is stretched at a high temperature; however, it needs a high extension ratio to promote the formation of void structures. As for annealing treatment, when the annealing temperature increased, the size and quantity of the spherulites that were formed in films by annealing also increased, but these films tend to have similar sizes and numbers of void structures. Based on the experimental results, this study also describes how parameters influence the void structures of a PP film created during the extension process. Analysis results further demonstrate how extension parameters and processing procedures can be adjusted to improve the fabrication of PP films.