Browsing by Author "Su, Hong-Yan"

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A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prufer Encoding
(2015-01-01)
Su, Hong-Yan
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Chen, Chieh-Chu
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Li, Yih-Lang
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Tu, An-Chun
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Wu, Chuh-Jen
As design-for-manufacturability techniques have become widely used to improve the yield of nano-scale semiconductor technology in recent years, hotspot detection methods have been investigated with a view to calibrating layout patterns that tend to reduce yield. In this paper, we propose two graph models, i.e., skeleton graph and space graph, to formulate polygon topology and spatial relationship among polygons. In addition, a Prufer encoding-based method is presented to encode each skeleton graph. Single polygon matching problem is then equivalent to the verification of graph isomorphism, which is realized by checking the identity of two enhanced Prfer codes associated with two skeleton grap. A branch and bound-based pattern anchoring algorithm is presented to resolve the vertex ordering problem for isomorphism checking. The general exact pattern matching problem can then be accomplished by adopting the space graph to identify the similarity of spatial relationship among polygons. Vias are one of the most device components that attract much attention in monitoring manufacturing variation due to via alignment issue, but hotspot detection rarely takes vias into consideration. Multilayer hotspot detection can also be realized by extending the skeleton graph to maintain the relations between adjacent layers through vias. Experimental results show that we can achieve 5.6x runtime speedup than design-rule-based methodology in average for single layer hotspot detection while the runtime for multilayer hotspot is roughly equal to the summation of that for individual single layer hotspot detection.
Clock Tree Aware Post-Global Placement Optimization
(2017-01-01)
Su, Hong-Yan
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Chiang, Po-Ting
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Samanta, Radhamanjari
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Li, Yih-Lang
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資訊工程學系
Power consumption is one of the key optimization objectives for modern integrated circuit designs. More than 40% of the total power consumption is contributed by clock trees due to their high frequency of switching and high capacitance. In the traditional physical design flow, placement is done before clock tree synthesis (CTS). CTS constructs a tree to connect the clock source with all the registers. Therefore, optimization of clock trees is limited by the quality of register placement. This paper proposes a post-global placement optimization procedure that integrates a fast three stage CTS method based on modified k-means clustering technique into a global placer. The fast three stage CTS constructs a virtual clock tree to guide global placement to favor CTS. Then a multi-level clock net contractive force according to the virtual clock tree is inserted to optimize register locations for reducing the clock tree wirelength. The experimental results show that the proposed optimization approach can reduce both the clock tree wirelength and clock net switching power at the cost of slight increase in half perimeter wirelength (HPWL).
MapReduce-Based Pattern Classification for Design Space Analysis
(2018-01-01)
Wu, Yan-Shiun
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Su, Hong-Yan
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Chang, Yi-Hsiang
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Topaloglu, Rasit Onur
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Li, Yih-Lang
With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapReduce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work outperforms the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.
Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs
(2017-01-01)
Su, Hong-Yan
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Nishizawa, Shinichi
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Wu, Yan-Shiun
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Shiomi, Jun
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Li, Yih-Lang
Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.
SubHunter: A High-Performance and Scalable Sub-Circuit Recognition Method with Prufer-Encoding
(2015)
Su, Hong-Yan
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Hsu, Chih-Hao
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Li, Yih-Lang
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資訊工程學系
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Department of Computer Science
Sub-circuit recognition (SR) is a problem of recognizing sub-circuits within a given circuit and is a fundamental component in simulation, verification and testing of computer-aided design. The SR problem can be formulated as subgraph isomorphism problem. Performance of previous works is not scalable as the complexities of modern designs increase. In this paper we propose a novel Prufer-encoding based SR algorithm that performs scalable and high-performance sub-circuit matching. Several techniques including tree structure partition, tree cutting and circuit graph encoding are proposed herein to decompose the SR problem into several small sub-sequence matching problems. A pre-filtering strategy is applied before matching to remove the sub-circuits that are not likely to be matched. A fast branch and bound approach is developed to identify all the sub-circuits within the given circuit. Experimental results show that SubHunter can achieve better performance than SubGemini and detect all the sub-circuits as well. As the circuit size increases, we can also achieve near linear runtime growth that outperforms the exponential growth for SubGemini, showing the scalability of the proposed algorithm.