Browsing by Author "Su, Hsin-Wen"

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A Unified 3D Device Simulation of Random Dopant, Interface Trap and Work Function Fluctuations on High-kappa/Metal Gate Device
(2011)
Li, Yiming
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Cheng, Hui-Wen
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Chiu, Yung-Yueh
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Yiu, Chun-Yen
;
Su, Hsin-Wen
In this work, we for the first time estimate total fluctuation resulting from random dopants (RDs), interface trap (ITs) and work functions (WKs) using experimentally calibrated 3D device simulation on 16-nm-gate high-kappa/metal gate devices. The total 3D simulated threshold voltage fluctuation (sigma V-th), induced by the aforementioned random sources simultaneously, is 55.5 mV for NMOS; however, a statistical total sum of these fluctuations is 12.3% overestimation because independence assumption on random variables is invalid owing to strong interactions among RDs, ITs and WKs. Device's DC/AC and CMOS SRAM circuit fluctuations have similar observation. FinFET-based structure innovation possessing large fluctuation suppression (sigma V-th = 30.2 mV; 45.6% reduction), compared with process efforts on planar one, is further discussed.
Nanosized metal grains induced electrical characteristic fluctuation in 16-nm-gate high-kappa/metal gate bulk FinFET devices
(2011-07-01)
Li, Yiming
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Cheng, Hui-Wen
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Yiu, Chun-Yen
;
Su, Hsin-Wen
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傳播研究所
In this work, the work function fluctuation (WKF) induced variability in 16-nm-gate bulk N-FinFET is for the first time explored by an experimentally calibrated 3D device simulation. Random nanosized grains of TiN gate are statistically positioned in the gate region to examine the associated carriers' transport, concurrently capturing "grain number variation" and "grain position fluctuation." The newly developed localized WKF simulation method enables us to estimate the threshold voltage fluctuation of devices with respect to the aspect ratio (AR = fin height/fin width) which accounts for the random grain's size, number and position effects simultaneously. (C) 2011 Elsevier B.V. All rights reserved.
On Statistical Variation of MOSFETs Induced by Random-Discrete-Dopants and Random-Interface-Traps
(2012)
Li, Yiming
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Su, Hsin-Wen
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Chen, Chieh-Yang
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Cheng, Hui-Wen
;
Chen, Yu-Yu
In this work, we statistically study characteristic fluctuation of 16-nm-gate high-kappa/metal gate (HKMG) MOSFETs by random-discrete-dopants (RDDs) inside silicon channel and random-interface-traps (RITs) at high-kappa/silicon interface. Randomly generated devices with three-dimensional (3D) RDDs inside device channel and 2D RITs at HfO2/Si interface are incorporated into quantum mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to RITs near the source and drain ends, and RDDs near the device channel surface and silicon substrate. Characteristic fluctuations are affected to different extents by the random combinatorial RDDs and RITs. Nonlinearly correlated RDDs and RITs further violate the statistical assumption of independent identical distributions between the RDDs- and RITs-induced random variables. Consequently, for the studied 16-nm-gate HKMG MOSFETs, the threshold voltage fluctuation induced by the combined RDs and ITs is less than their statistical sum due to local interaction of surface potentials resulting from the RDDs and RITs simultaneously. In contrast to RDDs fluctuation, the screening effect of device\'s inversion layer cannot effectively screen potential\'s variation resulting from RITs; thus, devices still have noticeable gate capacitance characteristic fluctuation under high gate bias.
Random Work Function Induced DC Characteristic Fluctuation in 16-nm High-kappa/Metal Gate Bulk and SOI FinFETs
(2012)
Su, Hsin-Wen
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Chen, Yu-Yu
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Chen, Chieh-Yang
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Cheng, Hui-Wen
;
Chang, Han-Tung
This work studies the metal gate\'s work function fluctuation induced DC characteristic fluctuation in the 16-nm bulk and silicon-on-insulator (SOI) fm-type field effect transistor (FinFET) devices using an experimentally calibrated 3D device simulation. The method of localized work function fluctuation simulation enables us to estimate local fluctuations including the nanosized grain\'s random effects of FinFET with TiN/HfO2 gate stacks. The result of this study shows characteristic fluctuation strongly depends upon the size of localized nanosized metal grains. The shape of grains does have marginal influence on device\'s variability.
The intrinsic parameter fluctuation on high-kappa/metal gate bulk FinFET devices
(2013-09-01)
Li, Yiming
;
Su, Hsin-Wen
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Chen, Yu-Yu
;
Hsu, Sheng-Chia
;
Huang, Wen-Tsung
In this work, based on the experimentally calibrated 3D device simulation, we for the first time estimate the impact of intrinsic parameter fluctuation on the electrical characteristic of 16-nm-gate TiN/HfO2 bulk FinFETs. The sources of intrinsic parameter fluctuation include the random discrete dopants, interface traps and work function differences, simultaneously. The full 3D simulated threshold voltage fluctuation, induced by the aforementioned random sources simultaneously, is 26.2 mV for the N-type bulk FinFET (and is 55.5 mV for the planar N-MOSFET). For the N-type bulk FinFE'T, the statistical sum of these fluctuations is 9.5% (and is 12.3% for the planar device) overestimation, compared with the full 3D simulation. One of the main reasons is the independence assumption on these random variables is destroyed owing to interactions to different extents among RDs, ITs and WKs. The coupled surface potentials cannot be simply estimated by using their statistical sum of individual random source. Under the same threshold voltage, compared with the result of the planar MOSFETs, more than 50% reduction on the threshold voltage fluctuation of the explored bulk FinFETs is observed owing to the benefit of 3D structural nature. (C) 2013 Elsevier B.V. All rights reserved.