Browsing by Author "Su, JG"

Now showing 1 - 7 of 7

A study of tilt angle effect on Halo PMOS performance
(1998-09-01)
Su, JG
;
Wong, SC
;
Huang, CT
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The Halo structure is usually adopted in deep submicrometer MOS devices for punchthrough prevention. The tilt angle of the Halo implant determines the dopant distribution which induces anti-punchthrough operation. In this paper, we investigate the impact of the tilt angle on the Halo PMOS device performance via two-dimensional (2D) simulations. We find that the ratio of on-current to off-current is constant for all tilt angles of Halo implant, implying an equivalent DC performance for all tilt angles. The equivalence can be traced back to a self compensation between the body factor and source resistance. The result :implies that a low tilt angle should be adopted for Halo devices, for it gives a small threshold voltage and thus a high noise margin. The methodology used in analyzing body factor and source resistance can also be applied to analyze other devices. (C) 1998 Elsevier Science Ltd. All rights reserved.
An investigation on RF CMOS stability related to bias and scaling
(2002-04-01)
Su, JG
;
Wong, SC
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In recent times, CMOS devices have played an increasing important role in the area of RF-ICs to implement part of the high-frequency circuits. As a result, the high-frequency characteristics of CMOS devices, including stability, should be investigated in-depth. In the design of RF amplifier, the consideration to avoid oscillation in the circuits is a must. Basically, the instability involved in designing RF circuits can be reduced if the transistor is stable in the interesting frequency region. In this study, the stability factor of CMOS device is discussed. First, the stability factor (i.e. k-factor) is derived based on the microwave small-signal model of MOSFET. Therefore, small-signal parameters that affect stability can be carefully examined. In addition, the effects of biasing and dimensions on k-factor are also discussed. Since various operating point (or biasing) can cause device to have different effects on high frequency, the correlation between biasing and stability is discussed in this study. Due to the fact that CMOS device has continuously shrunk in size, a detailed discussion of the effect of MOSFETs dimension on stability is included. It is found from our experimental results that the smaller the gate length, the greater is the frequency range for CMOS device to become potentially unstable. (C) 2002 Elsevier Science Ltd. All rights reserved.
Improving the RF performance of 0.18 mu m CMOS with deep n-well implantation
(2001-10-01)
Su, JG
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Hsu, HM
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Wong, SC
;
Chang, CY
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Huang, TY
The radio-frequency (RF) figures of merit of 0.18 mum complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F-t) and maximum oscillation frequency (F-max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible dc disturbance. Specifically, 18% increase in F-t and 25% increase in F-max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications.
Investigations of bulk dynamic threshold-voltage MOSFET with 65GHz "normal-mode" Ft and 220GHz "over-drive mode" Ft for RF applications
(2001)
Chang, CY
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Su, JG
;
Hsu, HM
;
Wong, SC
;
Huang, TY
The RF properties of bulk dynamic threshold-voltage MOSFET (B-DTMOS) with a deep n-well isolation was investigated both under the normal DTMOS mode and two newly-proposed DTMOS operation modes: moderate (0.6V < Vgs = Vbs < 0.85V) and over-drive (Vgs = Vbs > 0.85V) modes. While Ft can be improved to 65GHz at 12.5mA with 1.5V Vds bias under normal-mode DTMOS operation, a high Ft of 220GHz with good linearity and stability is achieved under over-drive mode of operation.
New insights on RF CMOS stability related to bias, scaling, and temperature
(2000)
Su, JG
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Wong, SC
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Chang, CY
;
Chiu, KY
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Huang, TY
The stability issues of CMOS devices for RF applications were studied. The stability factor of MOS devices based on the small-signal model (SSM) parameters was derived, for the first time. The results reveal some new insights on the effects of biasing, and scaling parameters on the stability; and were subsequently confirmed by our experimental results. Our results also show that unconditional stability of RF CMOS devices can be obtained with proper biasing and device geometries. Finally, the effects of temperature on stability were also: investigated. Our results suggest that careful attention needs to be paid for stable low temperature operation.
RF CMOS technology for MMIC
(2002-04-01)
Chang, CY
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Su, JG
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Wong, SC
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Huang, TY
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Sun, YC
This paper presents a high performance RF CMOS technology with a complete portfolio of RF and base band components for single-chip systems. Using an optimized 0.13 mum CMOS topology, f(T) of 86 GHz and f(max) of 73 GHz are obtained, in addition to a NFmin of 1.5 dB without ground-shielded signal pad. The high-Q accumulation-mode and diode varactors are optimized to perform a high tuning range of 47% and 25%, respectively. Inductors with a quality factor of 18 at 1.7 nH are obtained using copper interconnect, while capacitors with high unit capacitance and quality factor are fabricated with metal-insulator-metal structures. Finally, a deep n-well isolation is adopted to suppress the interblock coupling noise penetrating through substrate by 40 and 25 dB at 0.1 and 2.4 GHz, respectively. These results clearly demonstrate that CMOS technology can provide a complete solution for single-chip wireless systems. (C) 2002 Elsevier Science Ltd. All rights reserved.
The extraction of MOSFET gate capacitance from S-parameter measurements
(2002-08-01)
Su, JG
;
Wong, SC
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Chang, CY
;
Huang, TY
;
電子工程學系及電子研究所
A new gate capacitance extraction method from S-parameter measurements is proposed. The distributed nature of MOS transistor and the in-series substrate resistance and in-parallel gate conductance are taken into consideration in the gate capacitance extraction by using high-frequency S-parameter measurements. The error due to dissipation factor can be more effectively reduced by this method, compared to the conventional C-V measurements. Successful extraction of gate capacitance from test transistors with designed test pads has been demonstrated. (C) 2002 Elsevier Science Ltd. All rights reserved.