Browsing by Author "Su, JY"

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A modified HICUM model for GaInP/GaAs HBT devices
(2006-04-01)
Tseng, SC
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Meng, CC
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Chen, WY
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Su, JY
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電信工程研究所
A compact physics-based transit-time model is established for the GaInP/GaAs HBT device. The VBIC model fails to describe the transit-time frequency versus bias (I-C, V-CE), especially at low- and medium-current regimes. Starting with the HICUM model, we introduce a new time constant to describe the transit-time frequency versus bias (I-C, V-CE) more precisely. This model has obvious advantages over the VBIC model for showing the relation oj'f, versus bias (I-C, V-CE) in the low and medium current regimes for GaInP/GaAs HBT devices. (c) 2006 Wiley Periodicals, Inc.
A web data extraction description language and its implementation
(2005)
Wu, IC
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Su, JY
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Chen, TB
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資訊工程學系
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Department of Computer Science
A data extraction model, named the browser-oriented data extraction (BODE) model, was proposed in [14] to extract web contents with script functions. In this model, the system built on top of browsers accesses pages by simulating users' operations on browsers. Based on this model, this paper defines a scripting language, named the BODED (Browser-Oriented Data Extraction Description) language, which instructs the system how to do data extraction. This paper propose. a technique, called indirect browser replication to implement a BODE system, and also optimize the performance of this technique.
Analysis of DC characteristics and small signal equivalent circuit parameters of GaAs metal-semiconductor field effect transistors with different gate lengths and different gate contours by two-dimensional device simulations
(2005-09-01)
Meng, CC
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Su, JY
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Yang, SM
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電信工程研究所
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Institute of Communications Engineering
The gate length and gate contour of a GaAs metal-semiconductor field effect transistor (MESFET) device play important roles in determining the small signal circuit parameters and large signal breakdown voltage behavior, GaAs MESFETs with different gate lengths and gate contours were studied by the two-dimensional (2-D) semiconductor device simulations to investigate the dependence of small signal circuit parameters and breakdown voltage on gate length and gate contour. The results show that gate length affects small-signal circuit parameter C(gs) while gate contour affects C(gd). The breakdown voltage has strong dependence on gate contour and little dependence on gage length.
MPT-based branch-and-bound strategy for scheduling problem in high-level synthesis
(1998-11-01)
Hsiao, PY
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Wu, GM
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Su, JY
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
A branch-and-bound algorithm based on a maximum possibility table (MPT) is proposed to solve scheduling problems in high-level synthesis. Six efficient priority rules are developed as bounding functions in the algorithm. Extensions for real-world constraints are also considered, including chained operations, multicycle operations, mutually exclusive operations and pipelined data paths. Experimental results indicate that the MPT-based algorithm returns competitive scheduling results at significant savings in execution time as compared with other methods.
PLA-based Boolean factorization using ROBDD
(1995)
Hsiao, PY
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Liaw, RT
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Su, JY
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資訊工程學系
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Department of Computer Science
The effect of selectively and fully ion-implanted collector on RF characteristics of BJT devices
(2006-04-01)
Meng, CC
;
Su, JY
;
Tsou, BC
;
Huang, GW
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電信工程研究所
A selectively ion-implanted collector (SIC) is implemented in a 0.8 mu m BiCMOS process to improve the RF characteristics of the BJT devices. The SIC BJT device has better f(t) and f(max) than the FIC (fully ion-implanted collector) BJT device because the extrinsic base-collector capacitance is reduced by the SIC process. The f(t) is 7.8GHz and f(max) is 9.5 GHz for the SIC BJT device while the f(t) is 7.2 GHz and f(max) is 4.5 GHz for the FIC BJT device when biased at V-ce =3.6 V and J(c) = 0.07 mA/mu m(2). The noise parameters are the same for both BJT devices but the associated gain is higher for the SIC BJT device.
Using ordered binary decision diagrams to factorize multi-level logic
(1996)
Hsiao, PY
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Liaw, RT
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Su, JY
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交大名義發表
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資訊工程學系
A novel approach that employs ordered binary decision diagrams (OBDDs) is contributed to factorize multi-level logic functions by requiring as few literals as possible. A logic function with PLA format is represented as an OBDD form first. A heuristic decision method of variable ordering, called the order lookahead method, is derived for the construction of OBDDs. This method is based on the constant cofactor and the number of erasable logic terms for each input variable. The total execution time of the OBDD construction by the above ordering decisions is very fast for some MCNC benchmarks. With the above OBDDs, we introduce a simple yet effective graph manipulation, called EXT, to obtain a minimal number of literals in the Boolean function. This greedy EXT algorithm consists mainly of two phases. The first phase, called graph analysis,, identifies the similarities between nodes on the same level in the OBDD. The second phase, called tree analysis, utilizes the above features to extract the common parts of the nodes. The EXT procedure runs from the bottom level up to the top level of the OBDD. The computational complexity depends on the number of nodes in the OBDD. The results of simulations show that EXT has a very fast CPU execution time and a competitive literal ratio with other methods for some MCNC benchmarks. EXT will produce the smallest literal number, especially for structured or symmetric circuits.
Variable ordering for PLA-based ROBDD
(1995)
Su, JY
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Hsiao, PY
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資訊工程學系
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Department of Computer Science