Browsing by Author "Su, Jun-Ji"

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Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate
(2015-02-01)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Su, Jun-Ji
;
Shao, Chi-Shen
;
Thirunavukkarasu, Vasanthan
This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.
Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
(2014-12-11)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Su, Jun-Ji
;
Shao, Chi-Shen
;
Wang, Cheng-Ping
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (> 1 mu A/mu m). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I-on/I-off current ratio is over 10(8) A/A for L-g = 1 mu m. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V-th in multi-V-th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
High voltage characteristics of junctionless poly-silicon thin film transistors
(2013-09-16)
Cheng, Ya-Chi
;
Wu, Yung-Chun
;
Chen, Hung-Bin
;
Han, Ming-Hung
;
Lu, Nan-Heng
The breakdown voltage (V-BD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state V-BD of 53.4V is several times larger than V-BD of 9.5V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications. (C) 2013 AIP Publishing LLC.
Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel
(2014)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Shao, Chi-Shen
;
Su, Jun-Ji
;
Wu, Yung-Chun
The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high I-on/I-off current ratio (>10(7)) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.
Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor
(2014-08-13)
Cheng, Ya-Chi
;
Chen, Hung-Bin
;
Han, Ming-Hung
;
Lu, Nan-Heng
;
Su, Jun-Ji
The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitting experimental data exhibits the quantum confinement effect, indicating greater suppression of I-off than that in JL planar TFTs. The measured partial derivative V-th/partial derivative T of -1.34 mV/degrees C in JL GAA nanosheet TFTs has smaller temperature dependence than that of -5.01 mV/degrees C in JL planar TFTs.