Browsing by Author "Su, KC"

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Edge quantum yield in n-channel metal-oxide-semiconductor field-effect transistor
(2004-08-01)
Kang, TK
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Su, KC
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Chang, YJ
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Chen, MJ
;
Yeh, SH
The quantum yield of impact ionization is performed on an n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) by a carrier separation measurement. When the n-MOSFET is biased in accumulation, the carrier separation measurement demonstrates that the gate current mainly originates from the electrons injected into the underlying drain/source overlap regions. The measured substrate current is due to excess holes originating from the impact ionization of the injected electrons in the overlap regions. Therefore, the quantum yield in the overlap regions can be determined by the ratio of the substrate current to the gate current. It is well matched with the theoretical calculation of quantum yield. (C) 2004 American Institute of Physics.
Electromigration lifetime improvement of copper interconnect by cap/dielectric interface treatment and geometrical design
(2005-12-01)
Lin, MH
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Lin, YL
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Chen, JM
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Yeh, MS
;
Chang, KP
A significant improvement of electromigration (EM) lifetime is achieved by modification of the preclean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation prior to cap-layer deposition and adhesion of Cu/cap interface were found to be the critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration median-time-to-failure and activation energy. Effects of layout geometrical variation and stress current direction were also investigated.
Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology
(1998)
Ker, MD
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Chen, TY
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Wu, CY
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Tang, H
;
Su, KC
A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 Angstrom) of the input stage in a 0.25-mu m CMOS technology and sustain an ESD level above 2000V without extra process modification.
Plausible origin of electromigration lifetime extrapolation difference between wafer level isothermal test and package level constant current test
(2004)
Wang, CS
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Chen, MJ
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Chang, WC
;
Ke, WS
;
Lee, CF
Electromigration lifetime extrapolated from the wafer level isothermal test on a metal line does not coincide with that from the package level constant current test. The discontinuity of mass flux density in wafer level isothermal test as origin of such difference is identified based on a temperature profile along the metal line. Once this issue is clarified in advance, improved correlation between both tests can be achieved and as a result, wafer level isothermal test is expected to replace the conventional time-consuming package level constant current test.
RF noise characteristics of high-k AlTiOx and Al2O3 gate dielectrics
(2002-07-01)
Chen, SB
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Huang, CH
;
Chin, A
;
Lin, J
;
Jou, JP
We have characterized the radio frequency (rf) noise in high-k Al2O3 and AlTiOx gate dielectrics, which have respective effective oxide thickness (EOT) of 17.2 and 12.5 Angstrom. The measured noise figure in gate dielectric is material dependent and sensitive to dielectric defect after stress. Although the high-k AlTiOx gate dielectric has lower EOT, it has a higher noise figure than others. From the simulation in our proposed equivalent circuit model, the dominant noise is thermal noise and the reason for increasing noise figure after stress is due to additional parallel resistance by trap-assisted tunneling. (C) 2002 The Electrochemical Society.