Browsing by Author "Su, Kuan-Cheng"

Now showing 1 - 4 of 4

ESC robustness of 40-V CMOS devices with/without drift implant
(2006)
Chang, Wei-Jen
;
Ker, Ming-Dou
;
Lai, Tai-Hsiang
;
Tang, Tien-Hao
;
Su, Kuan-Cheng
The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased.
Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology
(2009)
Wang, Chang-Tzu
;
Ker, Ming-Dou
;
Tang, Tien-Hao
;
Su, Kuan-Cheng
;
電子工程學系及電子研究所
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49 mu mx21 mu m and consuming a very low standby leakage current of 96nA at room temperature.
Low-Trigger ESD Protection Design with Latch-Up Immunity for 5-V CMOS Application by Drain Engineering
(2017-01-01)
Chiang, Chun
;
Chang, Ping-Chen
;
Chao, Mei-Ling
;
Tang, Tien-Hao
;
Su, Kuan-Cheng
According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (V-BD) and low holding voltage (V-h) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency (V-t1=8.1V) without suffering from low V-BD and latch-up issues.
The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process
(2007)
Chang, Wei-Jen
;
Ker, Ming-Dou
;
Lai, Tai-Xiang
;
Tang, Tien-Hao
;
Su, Kuan-Cheng
The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated, that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.