Browsing by Author "Su, Ming-Chiuan"

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A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression
(2015-03-01)
Su, Ming-Chiuan
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Chen, Wei-Zen
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Wu, Pei-Si
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Chen, Yu-Hsiang
;
Lee, Chao-Cheng
A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI(pp) jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps(rms). The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm(2) only. It dissipates 12.4 mW from 1 V supply.
A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression
(2013-01-01)
Su, Ming-Chiuan
;
Chen, Wei-Zen
;
Wu, Pei-Si
;
Chen, Yu-Hsian
;
Lee, Chao-Cheng
A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1: 5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI(pp) input data jitter, the recovered clock jitter at 2GHz is 2.94ps(rms). The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200x150 mu m(2).
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs
(2015-04-01)
Su, Ming-Chiuan
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Jou, Shyh-Jye
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A low-jitter digitally controlled oscillator (DCO) with multiphase differential outputs and good linearity is presented. The DCO is composed of four differential delay cells and can achieve linear tuning over a wide frequency range. The proposed fully differential delay cell comprises logic cells in standard library and varactors. The measured rms jitter and pk-pk jitter from 2.5-GHz carrier are 2.827 and 29 ps, respectively. The power consumption is 6 mW from a 1.2 V supply. An experimental prototype is designed using 65-nm CMOS technology, and the chip area is 156 mu m x 92 mu m(2).
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
(2016-04-01)
Chang, Chia-Wen
;
Lo, Kai-Yu
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Ibrahim, Hossameldin A.
;
Su, Ming-Chiuan
;
Chu, Yuan-Hua
This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.