Browsing by Author "Su, N. C."

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A Low Operating Voltage ZnO Thin Film Transistor Using a High-kappa HfLaO Gate Dielectric
(2010)
Su, N. C.
;
Wang, S. J.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This study demonstrates the feasibility of producing a ZnO thin film transistor (TFT) using hafnium-lanthanum-oxide (HfLaO) as the gate dielectric. By integrating high-kappa HfLaO with an amorphous ZnO channel, the resulting HfLaO/ZnO TFTs display a low threshold voltage (V(T)) of 0.28 V, a small subthreshold swing (SS) of 0.26 V/dec, an acceptable mobility (mu(sat)) of 3.5 cm(2)/V s, and a good I(on)/I(off) ratio of 1 X 10(6). The SS heavily depends on the HfLaO/ZnO interface charges, a property which is related to the degree of crystallization of ZnO. The low VT and the small SS allow device voltage operation below 2 V for low power application. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3257607] All rights reserved.
Characteristics of Zinc Oxide Thin Film Transistors Fabricated by Location-Controlled Hydrothermal Method
(2010)
Yang, P. Y.
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Wang, J. L.
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Tsai, W. C.
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Wang, S. J.
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Chen, P. C.
In this paper, high-performance Zinc oxide (ZnO) thin-film transistors (TFTs) with bottom-gate (BG) structure and artificially location-controlled lateral grain growth have been prepared by low-temperature hydrothermal method. As the proper design of source/drain structure of ZnO/Ti/Pt thin films, the lateral grain growth can be artificially controlled in the desired location and the vertical grain boundary perpendicular to the current flow in the channel region can be reduced to single one. As compared with the conventional sputtered ZnO BG-TFTs, the proposed location-controlled hydrothermal ZnO BG-TFTs (W/L = 250 mu m/10 mu m) demonstrated the higher field-effect mobility of 6.09 cm(2)/V.s, lower threshold voltage of 3.67 V, larger on/off current ratio above 10(6), and superior current drivability, which can be attributed to the high-quality ZnO thin films with the reduced vertical grain boundaries in the channel region.
Flat band voltage control on low V(t) metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
;
Chang, M. F.
;
Lin, S. H.
;
Chen, W. B.
;
Lee, P. T.
The unwanted high threshold voltage (V(t)) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V(t) issue that is due to flat-band voltage (V(fb)) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V(fb) roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V(t) and good control of V(fb) roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
Flat band voltage control on low V-t metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
;
Chang, M. F.
;
Lin, S. H.
;
Chen, W. B.
;
Lee, P. T.
The unwanted high threshold voltage (V-t) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V-t issue that is due to flat-band voltage (V-fb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V-fb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V-t and good control of V-fb roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
High-Performance InGaZnO Thin-Film Transistors Using HfLaO Gate Dielectric
(2009-12-01)
Su, N. C.
;
Wang, S. J.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we report a low-voltage-driven amorphous indium-gallium-zinc oxide thin-film transistor with a high-k-value HfLaO gate dielectric. Good characteristics were achieved including a low V(T) of 0.22 V, small subthreshold swing of 76 mV/dec, high mobility of 25 cm(2)/V . s, and large I(on)/I(off) ratio of 5 x 10(7). These good performances are obtained at an operation voltage as low as 2 V. These characteristics are attractive for high-switching-speed and low-power applications.
HtLaON n-MOSFETs using a low work function HfSix gate
(2007-12-01)
Cheng, C. F.
;
Wu, C. H.
;
Su, N. C.
;
Wang, S. J.
;
McAlister, S. P.
At a 1.2-nm equivalent oxide thickness, HfSix/Hf0.7La0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm(2)/(V center dot s). These self-aligned and gate-first HfSix/Hf0.7La0.3ON n-MOSFETs were processed using standard ion implantation and 1000-degrees C rapid thermal annealing, making them fully compatible with current very large scale integration fabrication lines.
Low V-t gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection
(2008)
Liao, C. C.
;
Chin, Albert
;
Su, N. C.
;
Li, M. -F.
;
Wang, S. J.
We report low V-t Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phi(ro-eff) of 5.04 and 4.24 eV, low V-t of -0.16 and 0.13 V, high mobility of 85 and 209 cm(2)/Vs, and small 85 degrees C BTI <= 40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
Low V-t gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection
(2008-01-01)
Liao, C. C.
;
Chin, Albert
;
Su, N. C.
;
Li, M. -F.
;
Wang, S. J.
We report low V-t Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phi(m-eff) of 5.04 and 4.24 eV, low V-t of -0.16 and 0.13 V, high mobility of 85 and 209 cm(2)/Vs, and small 85 degrees C BTI <= 40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions
(2007)
Cheng, C. F.
;
Wu, C. H.
;
Su, N. C.
;
Wang, S. J.
;
McAlister, S. P.
We report very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good phi(m-eff) of 5.3 and 4.1 eV, low V(t) of +0. 05 and 0.03 V, high mobility of 90 and 243 cm(2)/Vs, and small 85 degrees C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.