Browsing by Author "Su, Ping-Hsun"

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A Systematic Approach to Correlation Analysis of In-Line Process Parameters for Process Variation Effect on Electrical Characteristic of 16-nm HKMG Bulk FinFET Devices
(2016-08)
Su, Ping-Hsun
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
This paper reports a systematic method to discover and optimize key fabrication in-line process of 16-nm high-kappa metal gate bulk FinFET to improve device\'s performance and variability. The sensitivity analysis is utilized to prioritize key in-line process parameters which significantly boost device\'s performance and effectively reduce its variations. To extract hidden correlations among complex and a large number of in-line process parameters, data mining technique is applied to highlight and group-associated in-line process parameters. The source of variations of in-line process parameters in each group is revealed and the optimized solution is proposed to reduce its sensitivity to devices\' fluctuation. Results show the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant are grouped to the same cluster and significantly affect the threshold voltage (V-t,V- sat), the on-state current (I-d,I- sat), and the off-state current (I-d,I- off), but the key variation source of these parameters is the thickness of the dual gate-spacer. By replacing dual spacers with single spacers, the fluctuation of threshold voltage is 30% dropped.
Analysis of In-Line Process Parameters of the Unity Gain Frequency of HKMG Bulk FinFET Devices
(2018-03-01)
Su, Ping-Hsun
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Li, Yiming
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電機工程學系
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Department of Electrical and Computer Engineering
This research explores the electrical characteristics of the unity gain frequency (F-t) in relation to the experimental in-line process parameters of 16-nm high-kappa metal gate bulk fin-type field effect transistor devices. Because F-t is dependent on the transconductance (G(m)) and effective gate capacitance (C-gg), a sensitivity analysis of these two factors is applied to determine key in-line process parameters. The engineering results of this letter indicate that G(m) and C-gg are significantly fluctuated by six in-line process parameters, including the gate length, fin height, high-kappa/interfacial layer thickness, source/drain (S/D) proximity, S/D depth, and gate height. These six parameters fluctuate F-t at the same time, withGm as the dominant factor.
Design Optimization of 16-nm Bulk FinFET Technology via Geometric Programming
(2014-01-01)
Su, Ping-Hsun
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Li, Yiming
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傳播研究所
;
Institute of Communication Studies
Design rule is an important interface between design and manufacturing. It becomes more complex as the process advances to 16-nm and beyond. Current approaches to generate design rules are empirical shrink and lithographic simulation. However, it is time-consuming and costly to revise design rules for performance boost and yield improvement after design rules are frozen. Early performance gains in early design rule development without cost increase and yield loss will benefit semiconductor industry. In this work, we for the first time consider 16-nm bulk FinFET standard cell performance, yield, area, and layout style simultaneously to optimize design rules to meet ITRS by using geometric programming. Optical proximity correction, and electromagnetic field and circuit simulations are performed for objective function evaluation. The result achieves more than 100%-delay and 50%-yield improvement without area change by this systematic and statistical approach.
Determination of Source-and-Drain Series Resistance in 16-nm-Gate FinFET Devices
(2015-05-01)
Su, Ping-Hsun
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
Source/drain (S/D) series resistance is difficult to extract, owing to poor epigrowth and nonuniform distribution of current density in S/D, critical limitation of restrictive design rule, ultrathin contact film, and complicated 3-D FinFET structure. In this brief, we, for the first time, propose a novel test structure for the measurement of the S/D series resistance. This technique enables us to determine the individual value of the S/D series resistance resulting from the S/D contact, the S/D epigrowth fin, and the channel gate, respectively. Each device\'s S/D series resistance on different layout locations is characterized on the basis of its connection with specified S/D contact. The test structure and extraction method can be applied to monitor the process development of sub-16-nm-gate multifin bulk FinFET devices, such as the channel fin doping, the S/D epigrowth, and the S/D contact size formation.
Exploration of Inter-Die Bulk Fin-Typed Field Effect Transistor Process Variation for Reduction of Device Variability
(2016-06)
Su, Ping-Hsun
;
Li, Yiming
;
交大名義發表
;
傳播研究所
;
電機學院
This work first reports a novel exploration technique to systematically prioritize key fabrication in-line process parameters of 16-nm high-k metal gate (HKMG) bulk FinFET to reduce device\'s die-to-die variation. To extract hidden correlations and reduce decision variables among the complex in-line process parameters, a data mining technique is employed to highlight and group associated parameters. To correlate the measured data with the distribution of physical dimension of devices for all in-line processes, a sensitivity analysis is then performed. Because the variability of current process deeply affects the next process, so the sequence of fabrication process is further added into the analyzing procedure to increase the searching efficiency. The source of variation of the initial process can be monitored and traced by the proposed methodology. The result of this study indicates that the gate spacer is a key process factor and will determine the uniformity of process including, such as the source-and-drain proximity, and the depth, lateral offset and overlap of sequential doping implants. The ranked key in-line process parameters can be used to optimize process and minimize the device variability of 16-nm HKMG bulk FinFET devices.
Impacts of plasma-induced damage due to UV light irradiation during etching on Ge fin fabrication and device performance of Ge fin field-effect transistors
(2017-02-01)
Mizubayashi, Wataru
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Noda, Shuichi
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Ishikawa, Yuki
;
Nishi, Takashi
;
Kikuchi, Akio
We investigated the impacts of plasma-induced damage due to UV light irradiation during etching on Ge fin fabrication and the device performance of Ge fin field-effect transistors (Ge FinFETs). UV light irradiation during etching affected the shape of the Ge fin and the surface roughness of the Ge fin sidewall. A vertical and smooth Ge fin could be fabricated by neutral beam etching without UV light irradiation. The performances of Ge FinFETs fabricated by neutral beam etching were markedly improved as compared to those of Ge FinFETs fabricated by inductively coupled plasma etching, in which the UV light has an impact. (C) 2017 The Japan Society of Applied Physics
Process Technological Analysis for Dynamic Characteristic Improvement of 16-nm HKMG Bulk FinFET CMOS Circuits
(2016)
Su, Ping-Hsun
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this work, we study dynamic characteristic of digital CMOS circuits of 16-nm HKMG bulk FinFET devices by optimizing fabrication windows of inline parameters. Key process parameters are ranked according to integrated circuit quiescent current (IDDQ) and delay of ring oscillators. IDDQ and delay are affected by the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant. Dependencies of operational frequency and IDDQ on the on-state current ratio of N/P FinFET devices are examined. By replacing dual spacers with single ones will improve the uniformity of implantation; consequently, the variation of IDDQ can be reduced from 252 to 37 nA significantly.
Process-Dependence Analysis for Characteristic Improvement of Ring Oscillator Using 16-nm Bulk FinFET Devices
(2016-08)
Su, Ping-Hsun
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we explore the electrical characteristics of ring oscillator (RO) by optimizing fabrication inline windows of 16-nm high-k/metal-gate bulk FinFET devices. Key process parameters are ranked according to ROs\' performance, including effective capacitance (C-eff), effective resistance (R-eff), and integrated circuit quiescent current (IDDQ). Process-dependence factors are then extracted and classified to reveal the actual root cause of each cluster. The findings of this paper indicate the dual gate spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant affect Ceff, Reff, and IDDQ significantly, but the variation source of these parameters is the thickness of the dual gate spacer. Furthermore, impacts of the ON-state current ratio of N/P devices on delay and IDDQ of RO are examined by replacing dual spacers with single ones, the uniformity of implantation can be enhanced. Thus, the fluctuation of IDDQ is seven times reduced (from 252 to 37 nA) and RO characteristic can fit to designing target.
Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices
(2015-05-01)
Su, Ping-Hsun
;
Li, Yiming
;
電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Effective extraction of source/drain (S/D) series resistance is a challenging task owing to poor epi-growth and nonuniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra thin contact film, and complicated 3-D fin-type field effect transistor (FinFET) structure. In this paper, we report a test structure for measurement of linear and nonlinear S/D series resistances. This technique enables us to evaluate each component of S/D series resistance resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate, respectively. The S/D series resistance for fins on different layout location of the same diffusion is characterized and modeled by connection with a specified S/D contact on it. Furthermore, the S/D series resistance of each fin can be analytically calculated, respectively, by swapping the S/D bias condition. The proposed test structure and extraction technique provides a robust monitoring tool to diagnose a process weak point of the 16-nm multifin high-k/metal gate bulk FinFET devices.