Browsing by Author "Sun, S. W."

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Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
(2009)
Chung, Steve S.
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Hsieh, E. R.
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Liu, P. W.
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Chiang, W. T.
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Tsai, S. H.
A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I(D.sat) current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%-1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover. PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable Reliability
(2008)
Chung, Steve S.
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Hsieh, E. R.
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Huang, D. C.
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Lai, C. S.
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Tsai, C. H.
In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyond
(2008)
Hsieh, E. R.
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Chung, Steve S.
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Lin, Y. H.
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Tsai, C. H.
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Liu, P. W.
In this work, for the first time, an abnormal leakage current has been observed in MOSFET with 50nm channel length and beyond. This effect shows that, in an ultra-short channel MOSFET, sub-threshold swing (SS) and I(off) are decreased for back-biased nMOSFET and pMOSFET. This effect is attributed to the BJT-induced current from the source to the drain. An experimental approach has been used to verify the existence of this BJT current component. As a consequence, this BIT current can be reduced with appropriate control of the S/D-to-substrate junction. As an application of the approach to advanced embedded-SiC MOSFET with various splits, it was found that a higher band-offset of S/D-to-substrate junction will give rise to a larger the BJT ballistic transport current. This provides us important information on reducing the leakage current for advanced CMOS with 50nm and beyond.
New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI Reliabilities for 65nm node CMOS devices and beyond
(2006)
Chung, Steve S.
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Huang, D. C.
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Tsai, Y. J.
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Lai, C. S.
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Tsai, C. H.
In this paper, new observations on the uniaxial and biaxial strain-induced hot carrier reliability and/or NBTI in nMOSFET and pMOSFET respectively have been reported for the first time. Uniaxial and biaxial strained nMOSFET and pMOSFET have been extensively examined. Different mechanisms are responsible for different strains in nMOSFET and pMOSFET. For the nMOFETs, it was found that uniaxial strain device has comparable HC reliability with the control device, while biaxial SiGe-strained device exhibits a much worse reliability. This is related to a large impact ionization rate in a biaxial strain which leads to a much worse reliability. For the pMOSFETs, either uniaxial or biaxial strained device shows a comparable amount of HC degradation, while SiGe S/D strained structure might be better considering process complexity, performance, and reliability Although NBTI is still a great concern in SiGe S/D devices, embedded SiGe S/D technique can improve greatly the device NBTI reliability. These results provide a valuable guideline for the present 65nm and beyond CMOS device design with focus on the strain engineering.
Technology roadmaps on the ballistic transport in strain engineered nanoscale CMOS devices
(2007)
Chung, Steve S.
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Tsai, Y. J.
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Tsai, C. H.
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Liu, P. W.
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Lin, Y. H.
As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the ION current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100nm regime.
The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientations
(2007)
Tsai, Y. J.
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Chung, Steve S.
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Liu, P. W.
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Tsai, C. H.
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Lin, Y. H.
The channel backscattering and injection velocity of carriers in advanced CMOS devices are the two key parameters for achieving high drain current enhancement. For the first time, an extensive study of these transport parameters for different substrate orientations has been evaluated for both nMOSFET and pMOSFET. By suitably choosing the substrate orientation, it may achieve a reduced backscattering and an increased injection velocity, which is preferable for designing high performance logic CMOS devices. Results show that, in pMOSFET, (110) substrate is preferred and current enhancement can be greatly enhanced in the < 112 > channel. In comparison, (110) substrate in nMOSFET has an adverse effect in reducing driving current as a result of poorer transport characteristics. Therefore, (100) substrate is expected for nMOSFET design. A guideline is then summarized for the optimum design of high performance CMOS devices.
The Observation of Trapping and Detrapping Effects in High-k Gate Dielectric MOSFETs by a New Gate Current Random Telegraph Noise (I(G)-RTN) Approach
(2008)
Chang, C. M.
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Chung, Steve S.
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Hsieh, Y. S.
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Cheng, L. W.
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Tsai, C. T.
A new method, called gate current Random Telegraph Noise (I(G) RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, I(G) RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the soft-breakdown (SBD) behavior of a device can be clearly identified. Its I(G) RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.
Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nm
(2006)
Lee, G. D.
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Chung, S. S.
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Mao, A. Y.
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Lin, W. M.
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Yang, C. W.
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1nm (EOT). With the scaling of gate oxide thickness into 1mn regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT = 10.2 angstrom) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide.