Browsing by Author "Sun, SW"

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A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering
(2005)
Chung, SS
;
Liu, YR
;
Wu, SJ
;
Lai, CS
;
Liu, YC
In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC(Hot Carrier) and NBT (Negative Bias Temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (I I 0)/(l 00) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/(100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices.
A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devices
(2005)
Chung, SS
;
Liu, YR
;
Yeh, CF
;
Wu, SR
;
Lai, CS
In this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge out-diffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.
Comparison of oxide breakdown progression in ultra-thin oxide SOI and bulk pMOSFETs
(2004)
Chan, CT
;
Kuo, CH
;
Tang, CJ
;
Chen, MC
;
Wang, TH
Accelerated oxide breakdown progression in ultra-thin oxide (1.4nm) SOI pMOSFETs is observed, as compared to bulk devices. The accelerated progression is explained by the increase of hole stress current as a result of breakdown induced channel carrier heating in a floating-body configuration. Numerical simulation of hole tunneling current and hot carrier luminescence measurement are carried out to justify the proposed theory.
Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range
(2004)
Chung, SS
;
Feng, HJ
;
Hsieh, YS
;
Liu, A
;
Lin, WM
A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Angstrom-16Angstrom range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate detennination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs
(2003)
Wang, TH
;
Tsai, CW
;
Chen, MC
;
Chan, CT
;
Chiang, HK
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4nm) pMOS is observed. This result is believed due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.
Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology
(1998)
Ker, MD
;
Chen, TY
;
Wu, CY
;
Tang, H
;
Su, KC
A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 Angstrom) of the input stage in a 0.25-mu m CMOS technology and sustain an ESD level above 2000V without extra process modification.
Shallow-trench isolation with raised-field-oxide structure
(2000-03-01)
Chen, CM
;
Chang, CY
;
Chou, JW
;
Lur, W
;
Sun, SW
This paper describes a novel shallow-trench isolation (STI) structure to suppress the corner metal-oxide semiconductor field-effect transistor (MOSFET) inherent to trench isolation. A gate oxide and a thin polysilicon layer are first processed, and are then followed by the STI process. With this raised-field-oxide structure, the anomalous subthreshold conduction of the shallow-trench isolated MOSFETs due to electric-field crowding at the active edge has been successfully eliminated. No inverse-narrow-width effect is observed as the device width has been scaled down to 0.3 mu m. The raised-field-oxide structure provides a larger process margin for planarization, and good device characteristics were achieved by this novel STI structure.