Browsing by Author "Sun, TP"

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A new CMOS readout circuit design for the IR FPA with adaptive gain control and current-mode background suppression
(1996)
Hsieh, CC
;
Wu, CY
;
Jih, FW
;
Sun, TP
;
Chang, H
A new cryogenic CMOS readout structure for infrared focal plane array
(1997-08-01)
Hsieh, CC
;
Wu, CY
;
Sun, TP
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50 x 50 mu m(2). Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. An experimental SCI readout chip has been designed and fabricated in 0.8-mu m double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12 x 10(8) electrons, a maximum transimpedance of 1 x 10(9) Omega, and ae active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's.
A new cryogenic CMOS readout structure for infrared focal plane array
(1997-08-01)
Hsieh, CC
;
Wu, CY
;
Sun, TP
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50 x 50 mu m(2). Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. An experimental SCI readout chip has been designed and fabricated in 0.8-mu m double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12 x 10(8) electrons, a maximum transimpedance of 1 x 10(9) Omega, and ae active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's.
Focal-plane-arrays and CMOS readout techniques of infrared imaging systems
(1997-08-01)
Hsieh, CC
;
Wu, CY
;
Jih, FW
;
Sun, TP
;
電子工程學系及電子研究所
A discussion of CMOS readout technologies fur infrared (IR) imaging systems is presented, First, the description of various types of IR detector materials and structures is given, The advances of detector fabrication technology and microelectronics process technology have led to the development of large format array of IR imaging detectors, For such large IR FPA's which is the critical component of the advanced infrared imaging system, general requirement and specifications are described, To support a good interface between FPA and downstream signal processing stage, both conventional and recently developed CMOS readout techniques are presented and discussed, Finally, future development directions including the smart focal plane concept are also introduced.
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA
(1998-08-01)
Hsieh, CC
;
Wu, CY
;
Sun, TP
;
Jih, FW
;
Cherng, YT
A new CMOS current readout structure for the infrared (IR) focal-plane-array (FPA), called the buffered gate modulation input (BGMI) circuit, is proposed in this paper. Using the technique of unbalanced current mirror, the new BGMI circuit can achieve high charge sensitivity with adaptive current gain control and good immunity from threshold-voltage variations. Moreover, the readout dynamic range can be significantly increased by using the threshold-voltage-independent current-mode background suppression technique. To further improve the readout performance, switch current integration techniques, shared-buffer biasing technique, and dynamic charging output stage with the correlated double sampling circuit are also incorporated into the BGMI circuit, An experimental 128 x 128 BGMI readout chip has been designed and fabricated in 0.8 mu m double-poly-double-metal (DPDM) n-well CMOS technology, The measurement results of the fabricated readout chip under 77K and 5 V supply voltage have successfully verified both readout function and performance improvement. The fabricated chip has the maximum charge capacity of 9.5 x 10(7) electrons, the transimpedance of 2.5 x 10(9) Omega at 10 nA background current, and the active power dissipation of 40 mW, The uniformity of background suppression currents can be as high as 99%. Thus, high injection efficiency, high charge sensitivity, large dynamic range, large storage capacity, and low noise can be achieved in the BGMI circuit with the pixel size of 50 x 50 mu m(2), These advantageous characteristics make the BGMI circuit suitable for various IR FPA readout applications with a wide range of background currents.