Browsing by Author "Sung, Gang-Neng"

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A Single-Inductor Programmable-Output (SIPO) DC-DC Converter for Low Power Applications
(2013)
Wey, Chin-Long
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Hsu, Chung-Hsien
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Sung, Gang-Neng
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents the first-ever single-inductor programmable-output (SIPO) DC-DC Converters. A SIPO converter is comprised of a DC-DC converter and a Phase-locked Loop (PLL). Based on the input frequency generated internally, the PLL provides the reference voltage for the converter to generate the desired voltage levels. To demonstrate the SIPO design concept, a voltage-mode boost DC-DC converter with a constant duty-cycle pulse control technique is implemented. For an input voltage of 1.5V, the boost converter is programmed to boost the output voltages to 2V to 4V over 90% power efficiency for the load currents ranged from 50mA to 300mA.
Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation
(2014-02-01)
Wey, Chin-Long
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Jui, Ping-Chang
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Sung, Gang-Neng
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電機工程學系
;
Department of Electrical and Computer Engineering
This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18 mu m CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.
MorSocket: An Expandable IoT-Based Smart Socket System
(2018-01-01)
Lin, Yi-Bing
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Huang, Chun-Ming
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Chen, Li-Kuan
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Sung, Gang-Neng
;
Yang, Chih-Chyau
Due to the flourishing development of the Internet of Things (IoT) technology, many smart home applications have become commercially available. One of the most popular applications is remotely controlled smart sockets. Most commercial smart socket products allow the user to control single-sockets. This paper proposes a smart socket system called MorSocket ("more sockets") that allows the user to control multiple separated sockets within a control webpage. These sockets share the same wireless communication module and therefore the hardware cost of MorSocket is lower than the single-socket solutions. Furthermore, by integrating MorSensor with an IoT management platform called IoTtalk, MorSocket can be automatically controlled by arbitrary sensors for temperature, humidity, UV, CO2, and so on. Such configuration is easily and flexibly set up through the IoTtalk GUI without extra programming efforts. We also develop the MorSensor system that provides multiple configurable sensors tailored to control MorSocket through simple plug-and-play. Then we investigate the user tolerance delay between when the user presses the on/off button and when he/she presses the next time if MorSocket does not respond. The user experience is poor if the MorSocket access delay is longer than the tolerance delay, and the user may keep pressing the button. We conduct measurements, analytic modeling, and simulation experiments to study the impact of the user tolerance delay. Our study observes the quick response of MorSocket, which results in excellent user experience.