Browsing by Author "Sung, HC"

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New triple self-aligned (SA3) split-gate flash cell with T-shaped source coupling
(2005-10-01)
Sung, HC
;
Lei, TF
;
Huang, CM
;
Kao, YC
;
Lin, YT
A new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling approach is described in this paper. This novel structure can significantly enhance coupling capacitance between the Source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6AV, which is characterized by a newly developed methodology for program vs disturb window characterization. For cell size scaling, comparable sort-1 and sort-2 yields are demonstrated using the new cell with a shorter floating length and a shallower source junction. To understand the relationship between source coupling ratio (SCR) and the program/erase mechanism, an insightful discussion on the program and erase mechanisms for our split-gate flash cell is also shown in this paper.
Novel program versus disturb window characterization for split-gate flash cell
(2005-03-01)
Sung, HC
;
Lei, TF
;
Hsu, TH
;
Kao, YC
;
Lin, YT
In this letter, a new methodology for program versus disturb window characterization on split gate Flash cell is presented for the first time. The window can be graphically illustrated in V-wI (word-line)-V-ss (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program, bias variations. This methodology was successfully implemented in 0.18-mum triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.
Novel single-poly EEPROM with damascene control-gate structure
(2005-10-01)
Sung, HC
;
Lei, TF
;
Hsu, TH
;
Wang, SW
;
Kao, YC
A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al2O3 grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-kappa material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.