Browsing by Author "Syu, Jin-Siang"

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15 GHz High-Isolation Sub-Harmonic Mixer With Delay Compensation
(2009-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-GHz high-isolation sub-harmonic mixer (SHM) with delay compensation is demonstrated in this letter using 0.35 mu m SiGe heterojunction bipolar transistor (HBT) technology. The proposed SHM consisting of two parallel stacked-LO mixer cores with opposite LO I/Q inputs substantially improves port-to-port isolation. A mathematical analysis regarding the isolation properties is also included in this letter. Further, a conventional stacked-LO SHM (w/o compensation) is also implemented with the same device sizes and bias conditions for a fair comparison. SHMs w/ and w/o compensation have similar conversion gain of 9/10 dB and noise figure of 14/13.5 dB when f(LO) = 7.5 GHz. However, the delay compensation technique improves the 2LO-RF/IF isolation by 34/35 dB, the LO-RF/IF isolation by 8/9 dB, and the RF-IF isolation by 22 dB.
16.4 GHz SiGe BiCMOS Sub-Harmonic Mixer With Reactive I/Q Generators in RF and LO Paths
(2009)
Tseng, Sheng-Che
;
Syu, Jin-Siang
;
Su, Jen-Yi
;
Wei, Hung-Ju
;
Meng, Chinchun
This paper demonstrates a high-frequency 0.35-mu m SiGe BiCMOS sub-harmonic downconverter with reactive in-phase and quadrature-phase (I/Q) generators. Two reactive I/Q generators are integrated in our work to provide differential quadrature RI and LO signals. The I/Q sub-harmonic downconverter with single-ended LO, RI, and IF (IM) ports has a conversion gain of 1 dB, IP(1dB) of -10 dBm, IIP(3) of 0 dBm and IIP(2) of 21 dBm at 16.4 GHz. The magnitude and phase errors between the I and Q channels are 1.34% and 0.6 degrees, respectively. The dc power consumption of this I/Q mixer without output buffers is approximately 5 mW.
2-GHz 1.35-dB NF pHEMT Single-Voltage-Supply Process-Independent Low-Noise Amplifier
(2018-01-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yang, Chun
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
A 2-GHz single-voltage-supply 0.15-mu m depletion-mode (D-mode) pseudomorphic high electron-mobility transistor (pHEMT) low-noise amplifier (LNA) is demonstrated with a proposed process-independent self-biasing scheme. The current-reused technique is also employed to achieve a common-source common-drain two-stage LNA under a dc current of 10.85 mA at a 3-V supply. As a result, the proposed LNA achieves 20-dB power gain and 1.35-dB noise figure (NF) at 2 GHz while the minimum NF=1.3 dB occurs at 2.4 GHz.
2.4-GHz 7.4-mW 300-kHz Flicker-Noise-Corner Direct Conversion Receiver Using 0.18 mu m CMOS and Deep-N-Well NPN BJT
(2013)
Chang, Wei-Ling
;
Meng, Chin-Chun
;
Syu, Jin-Siang
;
Wang, Chia-Ling
;
Huang, Guo-Wei
A low-power low-flicker-noise receiver is demonstrated using 0.18 mu m CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.
2.4-GHz Low-Noise Direct-Conversion Receiver With Deep N-Well Vertical-NPN BJT Operating Near Cutoff Frequency
(2011-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-mu m CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency (f(T)) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor f(T), the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has conversion gain of 51 dB and noise figure of 3.2 dB with 70-kHz 1/f noise corner, while the current consumption is 4.5 mA at a 1.8-V supply.
2.4/5.7 GHz dual-band high linearity gilbert upconverter utilizing bias-offset TCA and LC current combiner
(2007-12-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
電信工程研究所
;
Institute of Communications Engineering
A 2.4/5.7 GHz dual-band Gilbert upconversion mixer is demonstrated using 0.35 mu m SiGe BiCMOS technology. A bias-offset cross-coupled transconductance amplifier (TCA) is employed in the intermediate frequency port for the linearity improvement. The dual-band LC current combiner and the output shunt-shunt feedback buffer amplifier are in the radio frequency (RF) port. The mechanisms of the high linearity upconverter and, the design flow of the dual-band LC current combiner are established in this letter. The dual-band upconverter has conversion gain of 1.5/-0.2 dB, OP1dB of -10.5/-9 dBm, and OIP3 of 12/13 dBm for IF=100 MHz, RF= 2.4/5.7 GHz, respectively.
2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver-Hartley Image-Rejection Techniques
(2009-03-01)
Meng, Chin-Chun
;
Wu, Tzung-Han
;
Syu, Jin-Siang
;
Yu, Sheng-Wen
;
Tsung, Kuan-Chang
A 2.4/5.7-GHz dual-band Weaver-Hartley architecture, using 0.18-mu m CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver-Hartley architecture.
2.4/5.7-GHz Dual-Band Dual-Conversion Architecture With Correlated LO Signal Generators
(2009)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Wu, Tzung-Han
;
Huang, Guo-Wei
A 2.4/5.7-GHz dual-band dual-conversion downconverter is demonstrated using 0.35-mu m SiGe hetero-junction bipolar transistor (HBT) technology. This downconverter employs a complex dual-conversion system and a complex filter to reject the first and second image signals, respectively. The LO(1) frequency is 2.5 times the LO(2) frequency and is generated by a divide-by-two divider, a frequency doubler and a single-sideband up-converter. As a result, the correlated LO signals maintain excellent image-rejection performance of the dual-conversion system while only one LO input is needed. The downconverter achieves a 40/39-dB image-rejection ratio of the first image and a 44/46-dB image-rejection ratio of the second image for 2.4/5.7-GHz modes, respectively.
5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corner
(2012-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Syu, Jin-Siang
;
Lin, Chung-Yo
;
Wong, Shyh-Chyi
This paper demonstrates a low-power and low-flicker-noise direct-conversion receiver using double-balanced passive mixer. The deep-n-well vertical-NPN bipolar junction transistor is placed as at the input stage of the IF amplifier to reduce the flicker noise in the 0.18 um standard CMOS process. As a result, conversion gain achieves 50-dB gain when the LO power is 10 dBm and the noise figure is 7-dB at 100 kHz. The totally power consumption is 9.4 mW at 1.8 V voltage supply.
5.7 GHz Gilbert I/Q downconverter integrated with a passive LO quadrature generator and an RF Marchand balun
(2008-02-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yen, Ying-Chieh
;
電信工程研究所
;
Institute of Communications Engineering
A 5.7 GHz I/Q downconversion mixer is demonstrated in this letter using 0.35 mu m SiGe BiCMOS technology. A quarter-wavelength coupled line and two center-tapped transformers are utilized to generate differential quadrature LO signals. A miniaturized Marchand balun is placed before the common-base-configured RF input stage of each I/Q Gilbert mixer to generate balanced RF signals. All the reactive passive elements are placed directly on the standard silicon substrate. The 5.7 GHz I/Q downconverter achieves 7 dB conversion gain, -26 dBm IP1dB, and -18 dBm IIP3 at the power consumption of 3.875 mW and 2.5 V supply voltage.
9.9-mA 5-6 GHz CMOS Sub-Harmonic Direct-Conversion Receiver Using Deep N-Well BJT
(2014-01-01)
Chang, Wei-Ling
;
Meng, Chin-Chun
;
Syu, Jin-Siang
;
Wang, Chia-Ling
;
Huang, Guo-Wei
A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 mu m CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.
A 0.6-V 30 GHz CMOS Quadrature VCO Using Microwave 1:1:1 Trifilar Transformer
(2012-02-01)
Syu, Jin-Siang
;
Lu, Hsi-Liang
;
Meng, Chinchun
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 30 GHz trifilar-transformer-coupled quadrature voltage-controlled oscillator (QVCO) is proposed in this letter using 0.13 mu m CMOS technology. The trifilar transformer provides dc decoupling as well as ac mutual coupling from drain, gate, and source nodes. The mutual coupling increases the overall quality factor while the gate/drain-to-source coupling provides quadrature coupling. The proposed 1:1:1 trifilar transformer realization has lower ohmic loss than the conventional trifilar transformer realization and is especially suitable for high-frequency applications. As a result, the proposed 30 GHz QVCO has a -195 dBc/Hz figure of merit (FOM) and a maximum 41.6 dB sideband rejection (SBR) at a 0.6 V supply.
A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver
(2013-02-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-mu m CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below +/-0.2 dB/+/-1 degrees, respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply.
A Wideband SiGe HBT Gilbert Micromixer With Differential-to-Single CE-CC Output Stage
(2007)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wu, Chih-Kai
;
Huang, Guo-Wei
;
電信工程研究所
A wideband downconversion mixer is demonstrated using 0.35-mu m SiGe heterojunction bipolar transistor (HBT) technology. A micromixer topology is implemented in the RF port while a differential type shunt-shunt feedback amplifier and a differential-to-single CE-CC output buffer are used in the IF stage. ne frequency response analysis and systematic measurement approach for a wideband Gilbert mixer are proposed in this paper for each individual stage of local frequency (LO), radio frequency (RF), and intermediate frequency (IF). ne differential LO signals are generated by several off-chip 180 degree hybrids to cover more than 8:1 bandwidth. The downconversion Gilbert mixer achieves the conversion gain of 6 dB, IP(1dB) of -17.5 dBm, and IP(3) of -7 dBm. The power consumption is 37.5 mW at 3.3V supply voltage.
Analysis and Design of the 0.13-mu m CMOS Shunt-Series Series-Shunt Dual-Feedback Amplifier
(2009-11-01)
Wu, Tzung-Han
;
Syu, Jin-Siang
;
Meng, Chin-Chun
;
電子工程學系及電子研究所
;
電信工程研究所
This paper demonstrates the design methodology of the shunt-series series-shunt dual-feedback Meyer wideband amplifier. The small-signal S-parameters are obtained for the first time using the pole-and-zero analysis, thus giving the RF designers a detailed insight into the Meyer amplifier. A 10-GHz wideband amplifier is demonstrated in this paper, using 0.13-mu m CMOS technology to verify our design theory. The experimental results of the S-parameters highly agree with our theory.
Characteristics of GaAs transformers for RFIC applications
(2008-11-01)
Meng, Chinchun
;
Teng, Ya-Hui
;
Syu, Jin-Siang
;
Lin, Yi-Chen
;
Jhong, Jhin-Ci
In this article, stacked transformers, coupling stacked transformers, interleave transformers, and symmetrical transformers on GaAs substrate are systematically studied. Two kinds of stacked transformer are under study. One has the symmetrical electric property while the other one has a better quality factor for the primary port. The stack transformers have achieved the highest coupling coefficient (similar to 0.9) at the cost of lower self-resonance frequency. The interleave transformers have the identical electrical properties for the primary and the secondary ports. However, the layout is incompatible with the differential operation. Oil the other hand, the symmetrical transformer is compatible with the differential operation (aid call have the center-tapped biasing option. The data established here provides a useful design library for the GaAs RFIC. (C) 2008 Wiley Periodicals, Inc.
Comparison of wideband Gilbert micromixers using SiGe HBT and GaInP/GaAs HBT technologies
(2008-09-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wu, Chih-Kai
;
Huang, Guo-Wei
;
電信工程研究所
Wideband downconversion mixers are demonstrated by using both 0.35-mu m SiGe heterojunction bipolar transistor (HBT) and 2-mu m GaInP/GaAs HBT technologies. A micromixer topology is implemented in the RF port while a differential type shunt-shunt feedback amplifier and a differential-to-single CE-CC output buffer are used in the IF stage. The frequency response analysis and systematic measurement approach for a wideband Gilbert mixer are proposed in this article for each individual stage of local frequency (LO), radio frequency (RF), and intermediate frequency (IF). The differential LO signals are generated by several off-chip 180 degrees hybrids to cover more than 8:1 bandwidth. The SiGe HBT Micromixer achieves the conversion gain of 6 dB, IP(IdB) of -17.5 dBm, and IIP(3) of - 7 dBm with the 3.3-V supply voltage and the power consumption of 37.5 mW. On the other hand, the GaInP/GaAs HBT Micromixer achieves the conversion gain of 25 dB, IP(IdB) of -25 dBm, and IIP(3) of - 15 dBm with the 5-V supply voltage and the power consumption of 50 mW. (c) 2008 Wiley Periodicals, Inc.
Comparison on mHEMT Q-Band Sub-Harmonic Mixers With/Without Delay Compensation
(2010)
Syu, Jin-Siang
;
Meng, Chinchun
;
Su, Jen-Yi
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
Q-band sub-harmonic mixers (SHMs) with and without delay compensation are demonstrated in this paper using 0.15-mu m metamorphic high electron mobility transistor (mHEMT) technology. A conventional stacked-LO sub-harmonic mixing cell consists of two Gilbert cells in cascode with quadrature LO inputs. The proposed compensation core in parallel with the stacked-LO core improves the port-to-port isolation. A Marchand balun is employed at the RF port to generate wideband differential signals. As a result, SHMs w/ and w/o compensation achieve the conversion gain of 1/0.5 dB and noise figure of 23/20 dB when 2f(LO)=39/42 GHz. However, the compensation circuit improves the 2LO-to-RF isolation by 12 dB, 2LO-to-IF isolation by 5 dB and RF-to-IF isolation by 5 dB without additional power consumption.
Dual-Band Upconversion Gilbert Mixer Utilizing an LC Current Mirror
(2008)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yen, Ying-Chieh
;
Huang, Guo-Wei
;
電信工程研究所
Dynamic Range Reduction Due to RF and Image Signal Co-Existence in a Highly-Merged 2.4/5.7-GHz Dual-Band Low-IF Downconverter
(2010-01-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A highly-merged 2.4/5.7-GHz dual-band low-IF downconverter is demonstrated using 0.18-mu m CMOS technology. Weaver and Hartley architectures are utilized to achieve high image-rejection ratio (IRR) of first and second image signals. The first LO (LO(1)) is set exactly halfway between the two bands. That is, the 2.4/5.7-GHz bands are the first image signal of each other. However, in a real home/commercial environment, a 5.7/2.4-GHz blocking signal is present when the 2.4/5.7-GHz band is desired and degrades the dynamic range of the receiver. Therefore, the dynamic range degradation due to the co-existence of RF and image signals is discussed in this paper.