Browsing by Author "Sze, S. M."

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A comprehensive study of enhanced characteristics with localized transition in interface-type vanadium-based devices
(2020-06-01)
Lin, C. -Y.
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Chen, P. -H.
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Chang, T. -C.
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Huang, W. -C.
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Tan, Y. -F.
In this research, we investigated the conduction mechanism in metal-insulator transition (MIT) materials. Among these MIT materials (NbOx, NiOx, VOx, and TaS2), vanadium oxide-based selectors have been widely investigated because of their high switching speed (similar to 10-ns transition time), sufficient nonlinearity (>10(3)), and endurance stability (similar to 10(10)). Abnormal temperature-dependent degradation in the high resistive state was observed, as was studied in detail by a current fitting analysis and explored theoretically by electric (E-MIT) and thermal (T-MIT) modeling. The results suggest the existence of a MIT region located between the electrode and the localized filament. To improve the localized transition efficiency, we propose an enhanced-type MIT architecture to bypass the E-MIT and T-MIT universal rule with the novel structure of vanadium top electrode device. As compared with a vanadium oxide middle-layer device, the electrical transition efficiency is improved 2-fold as evidenced by thermal cycling material analysis, as well as boosting endurance reliability to 10(7) at 65 degrees C. Finally, for the first time, a potential neuromorphic computing application featuring a damping oscillator has been demonstrated in this enhanced-type MIT architecture, with a high damping ratio with 10-fold smaller area and 5-fold smaller energy than complementary metal-oxide-semiconductor (CMOS) devices. This presents a promising milestone for ultralow power neuromorphic system design and solutions in the near future. (C) 2020 Elsevier Ltd. All rights reserved.
A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
(2007-09-01)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
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Lin, Po-Shun
In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V-th), and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.
Bipolar resistive switching of chromium oxide for resistive random access memory
(2011-08-01)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Chen, Shih-Yang
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Chen, Chi-Wen
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Chen, Shih-Ching
This study investigates the resistance switching characteristics of Cr(2)O(3)-based resistance random access memory (RRAM) with Pt/Cr(2)O(3)/TiN and Pt/Cr(2)O(3)/Pt structures. Only devices with Pt/Cr(2)O(3)/TiN structure exhibit bipolar switching behavior after the forming process because TiN was able to work as an effective oxygen reservoir but Pt was not. Oxygen migration between Cr(2)O(3) and TiN was observed clearly before and after resistance switching from Auger electron spectroscopy (AES) analysis. Both low resistance state, ON state, and high resistance state, OFF state, of Pt/Cr(2)O(3)/TiN structures are stable and reproducible during a successive resistive switching. The resistance ratio of ON and OFF state is over 10(2), on top of that, the retention properties of both states are very stable after 10(4) s with a voltage of -0.2 V. (C) 2010 Elsevier Ltd. All rights reserved.
Carrier Transport and Multilevel Switching Mechanism for Chromium Oxide Resistive Random-Access Memory
(2011)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Chen, Shih-Yang
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Li, Hung-Wei
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Tsai, Yu-Ting
This article investigates the carrier transport phenomenon and multilevel switching mechanism of Cr(2)O(3)-based resistive random access memory (RRAM) with Pt/Cr(2)O(3)/TiN structure. Before the forming process, the interfacial Schottky barrier dominates the carrier transport. The barrier heights of Pt/Cr(2)O(3) and Cr(2)O(3)/TiN are 0.7 and 0.96 eV, respectively. After the forming process, RRAM at a low resistance state follows the Ohmic conduction. While RRAM is switched to a high resistance state during the reset process, the Frenkel-Poole emission becomes a dominant conduction mechanism. The multilevel resistance states were achieved by applying corresponding reset voltages to the device for controlling the trap levels of the Cr(2)O(3) layer. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3518710] All rights reserved.
Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure
(2007-12-15)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
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Lin, Po-Shun
In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V-th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V-th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V-th shift is improved from -0.3 V to -1.3 V at -14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 degrees C and a 0.8 V memory window after 5 x 10(3) P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display. (C) 2007 Elsevier B.V. All rights reserved.
Effects of postgate dielectric treatment on germanium-based metal-oxide-semiconductor device by supercritical fluid technology
(2010-03-15)
Liu, Po-Tsun
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Huang, Chen-Shuo
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Huang, Yi-Ling
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Lin, Jing-Ru
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Cheng, Szu-Lin
Supercritical fluid (SCF) technology is employed at low temperature as a postgate dielectric treatment to improve gate SiO(2)/germanium (Ge) interface in a Ge-based metal-oxide-semiconductor (Ge-MOS) device. The SCF can transport the oxidant and penetrate the gate oxide layer for the oxidation of SiO(2)/Ge interface at 150 degrees C. A smooth interfacial GeO(2) layer between gate SiO(2) and Ge is thereby formed after SCF treatment, and the frequency dispersion of capacitance-voltage characteristics is also effectively alleviated. Furthermore, the electrical degradation of Ge-MOS after a postgate dielectric annealing at 450 degrees C can be restored to a extent similar to the initial state.
Formation and nonvolatile memory characteristics of multilayer nickel-silicide NCs embedded in nitride layer
(2008-11-01)
Chen, Wei-Ren
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Chang, Ting-Chang
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Yeh, Jui-Lung
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Sze, S. M.
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Chang, Chun-Yen
The authors provided the formation and memory effects of nonvolatile multilayer nickel-silicide nanocrystal memory in this study. This proposed structure can efficiently improve the drawbacks of current floating gate and single-layer nanocrystal memories for the next-generation nonvolatile memory application. The charge trapping layer of multilayer structure was deposited by sputtering a commixed target (Ni(0.3)Si(0.7)) in the argon and nitrogen ambiance, and then used a low temperature rapid thermal annealing to form uniform nanocrystals. Transmission electron microscope images clearly show the multilayer and single-layer nanocrystal structures embedded in SiN(x). X-ray photoelectron spectroscopy and x-ray diffraction also present the chemical states and crystallization of nanocrystals under different annealing temperature treatments. The capacitor with different memory structures was also studied and exhibited hysteresis characteristics after electrical operation. In addition, the multilayer nanocrystals revealed better charge storage ability and reliability than the single-layer nanocrystals. (C) 2008 American Institute of Physics. [DOI: 10.1063/1.3006126]
Formation and nonvolatile memory characteristics of W nanocrystals by in-situ steam generation oxidation
(2010-12-30)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Hsieh, Chieh-Ming
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Li, Hung-Wei
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Sze, S. M.
The authors provide the formation and memory effects of W nanocrystals nonvolatile memory in this study. The charge trapping layer of stacked a-Si and WSi(2) was deposited by low pressure chemical vapor deposition (LPCVD) and was oxidized by in-situ steam generation system to form uniform W nanocrystals embedded in SiO(2). Transmission electron microscopy analyses revealed the microstructure in the thin film and X-ray photon-emission spectra indicated the variation of chemical composition under different oxidizing conditions. Electrical measurement analyses showed the different charge storage effects because the different oxidizing conditions influence composition of trapping layer and surrounding oxide quality. Moreover, the data retention and endurance characteristics of the formed W nanocrystal memory devices were compared and studied. The results show that the reliability of the structure with 2% hydrogen and 98% oxygen at 950 degrees C oxidizing condition has the best performance among the samples. (C) 2010 Elsevier B.V. All rights reserved.
Implementation of Functionally Complete Boolean Logic and 8-bit Adder in CMOS Compatible 1T1R RRAMs for In-Memory Computing
(2018-01-01)
Wang, Z. R.
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Li, Y.
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Su, Y. T.
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Zhou, Y. X.
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Yin, K. S.
RRAM is a promising candidate to construct in-memory computing architecture which can break through the von Neumann bottleneck. Taking advantage of the CMOS compatible 1T1R RRAM, functionally complete Boolean logics can be realized within two steps in a single unit that can suppress sneak pass problem and avoid cascading problem partially. In addition, an 8-bit pre-calculation adder with low computation complexity is designed and demonstrated experimentally to verify the feasibility and efficiency of 1T1R based in-memory computing architecture, which is applicable to future energy-efficient information processing systems.
Influence of hydrogen plasma treatment on charge storage characteristics in high density tungsten nanocrystal nonvolatile memory
(2011-03-31)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Chen, Wei-Ren
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Lo, Yuan-Chun
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Wu, Kai-Ting
This study focuses on the influence of a hydrogen plasma treatment on electrical properties of tungsten nanocrystal nonvolatile memory. The X-ray photon emission spectra show that, after the hydrogen plasma treatment, a change in binding energy occurs such that Si(x+) and Si(y+) peaks appear at a position that is shifted about 2.3 and 3.3 eV from Si(o+) in Si 2p spectra. This indicates that Si dangling bonds are passivated to form a Si-H bond structure in the SiO(2). Furthermore, the transmission electron microscopy shows cross-sectional and plane-view for the nanocrystal microstructure after the hydrogen plasma treatment. Electrical measurement analyses show improved data retention because the hydrogen plasma treatment enhances the quality of the oxide surrounding the nanocrystals. The endurance and retention properties of the memory device are improved by about 36% and 30%, respectively. (C) 2011 Elsevier By. All rights reserved.
Investigating the improvement of resistive switching trends after post-forming negative bias stress treatment
(2011-09-26)
Tseng, Hsueh-Chih
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Chang, Ting-Chang
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Huang, Jheng-Jie
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Yang, Po-Chun
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Chen, Yu-Ting
This paper investigates the improvement of resistive switching trends after post-forming negative bias stress treatment of a Pt/Yb(2)O(3)/TiN device that has undergone positive bias forming process for activation. After the treatment, characteristics of the conductive filament, such as the temperature dependence of resistivity and transition mechanism, undergo changes. Furthermore, this treatment causes the conductive filament to transform from being primarily composed of vacancies to being metallic Yb dominant, which not only reduces operation voltages such as V(set) and V(reset) but also improves the on/off ratio. In reliability tests, the device has stable retention. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3645004]
InZnSnO-Based Electronic Devices for Flat Panel Display Applications
(2014)
Liu, Po-Tsun
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Fuh, Chur-Shyang
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Fan, Yang-Shun
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Sze, S. M.
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交大名義發表
This work demonstrates the versatility of amorphous InZnSnO (a-IZTO) oxide semiconductor, covering from the thin film transistor (TFT) to the resistive random accessmemory (RRAM) technologies for system-on-panel applications. The high-performance a-IZTO TFTs with effective carry mobility of 39.6 cm(2)/V s, threshold voltage of -0.28 V and subthreshold swing of 0.25 decade/V are obtained in this study. Thermal post-annealing also was used to provide stable electrical characteristics with a few threshold voltage shift after positive gate bias stress. On the other hand, the RRAM device with a-IZTO film acting as active layer exhibits superior bipolar resistive switching characteristics. The wide (>10) resistance window and the stability endurance of hundreds cycle are achieved. Both of the proposed a-IZTO TFT and RRAM have promising potential to be integrated with a-IZTO-based periphery electronic circuits for flat-panel display applications. (c) 2014 The Electrochemical Society. All rights reserved.
Memory characteristics of Co nanocrystal memory device with HfO(2) as blocking oxide
(2007-03-26)
Yang, F. M.
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Chang, T. C.
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Liu, P. T.
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Yeh, P. H.
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Yu, Y. C.
In this letter, the Co nanocrystals using SiO(2) and HfO(2) as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window was estimated to similar to 1 V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 10(6) write/erase cycles. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry. (c) 2007 American Institute of Physics.
Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide
(2007-03-26)
Yang, F. M.
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Chang, T. C.
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Liu, P. T.
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Yeh, P. H.
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Yu, Y. C.
In this letter, the Co nanocrystals using SiO2 and HfO2 as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window was estimated to similar to 1 V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 10(6) write/erase cycles. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry. (c) 2007 American Institute of Physics.
Nickel nanocrystals with HfO2 blocking oxide for nonvolatile memory application
(2007-05-28)
Yang, F. M.
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Chang, T. C.
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Liu, P. T.
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Chen, U. S.
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Yeh, P. H.
A distributed charge storage with Ni nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated in this study. The mean size and aerial density of the Ni nanocrystals are estimated to be about 5 nm and 3.9x10(12)/cm(2), respectively. The nonvolatile memory device with Ni nanocrystals exhibits 1 V threshold voltage shift under 4 V write operation. The device has a long retention time with a small charge lose rate. Besides, the endurance of the memory device is not degraded up to 10(6) write/erase cycles. (C) 2007 American Institute of Physics.
Nickel silicide nanocrystals embedded in SiO2 and HfO2 for nonvolatile memory application
(2007-12-03)
Yang, F. M.
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Chang, T. C.
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Liu, Po-Tsun
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Yeh, Y. H.
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Yu, Y. C.
In this study, a nonvolatile memory device with NiSi2 nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated. A significant memory effect is observed during the characterization of the electrical properties. When a low operating voltage, 4 V, is applied, a significant threshold voltage shift of 1.3 V, is observed. The processing of this structure is compatible with the current manufacturing technology of semiconductor industry. (C) 2007 Published by Elsevier B.V.
Nonvolatile memory effect of tungsten nanocrystals under oxygen plasma treatments
(2010-10-01)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Chen, Wei-Ren
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Lo, Yuan-Chun
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Wu, Kai-Ting
In this work, an oxygen plasma treatment was used to improve the memory effect of nonvolatile W nanocrystal memory, including memory window, retention and endurance. To investigate the role of the oxygen plasma treatment in charge storage characteristics, the X-ray photon-emission spectra (XPS) were performed to analyze the variation of chemical composition for W nanocrystal embedded oxide both with and without the oxygen plasma treatment. In addition, the transmission electron microscopy (TEM) analyses were also used to identify the microstructure in the thin film and the size and density of W nanocrystals. The device with the oxygen plasma treatment shows a significant improvement of charge storage effect, because the oxygen plasma treatment enhanced the quality of silicon oxide surrounding the W nanocrystals. Therefore, the data retention and endurance characteristics were also improved by the passivation. (C) 2010 Elsevier B.V. All rights reserved.
Nonvolatile memory effect of tungsten nanocrystals under oxygen plasma treatments
(2010-10-01)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Chen, Wei-Ren
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Lo, Yuan-Chun
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Wu, Kai-Ting
In this work, an oxygen plasma treatment was used to improve the memory effect of nonvolatile W nanocrystal memory, including memory window, retention and endurance. To investigate the role of the oxygen plasma treatment in charge storage characteristics, the X-ray photon-emission spectra (XPS) were performed to analyze the variation of chemical composition for W nanocrystal embedded oxide both with and without the oxygen plasma treatment. In addition, the transmission electron microscopy (TEM) analyses were also used to identify the microstructure in the thin film and the size and density of W nanocrystals. The device with the oxygen plasma treatment shows a significant improvement of charge storage effect, because the oxygen plasma treatment enhanced the quality of silicon oxide surrounding the W nanocrystals. Therefore, the data retention and endurance characteristics were also improved by the passivation. (C) 2010 Elsevier B.V. All rights reserved.
Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels
(2007-03-19)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
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Yeh, Ping-Hung
In this work, the authors study a polycrystalline silicon thin-film transistor (poly-Si TFT) with oxide/nitride/oxide (ONO) stack gate dielectrics and multiple nanowire channels for the applications of both nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory and switch transistor. The proposed device named as nanowire SONOS-TFT has superior electrical characteristics of a transistor such as on/off current ratio, threshold voltage (V-th), and subthreshold slope due to the good gate control ability originated from fringing electrical field effects. Moreover, the proposed device under adequate operation scheme can exhibit high program/erase efficiency and good retention time characteristics at high temperature. (c) 2007 American Institute of Physics.
Nonvolatile Si/SiO2/SiN/SiO2/Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasing characteristics
(2007-11-05)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
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Chin, Jing-Yi
A silicon-oxide-nitride-oxide-silicon type polycrystalline silicon thin-film transistor (poly-Si TFT) with nanowire channels was investigated for both transistor and memory applications. The poly-Si TFT memory device has superior electrical characteristics, such as higher drain current, smaller threshold voltage, and steeper subthreshold slope. Also, the simulation result on electrical field reveals that the electrical field across the tunnel oxide is enhanced and that across the blocking oxide is reduced at the corner regions. This will lead to the parasitic gate injection activity and the erasing speed can be apparently improved in the memory device due to the pronounced corner effect and narrow channel width.