Browsing by Author "THAPAR, HK"

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A 30-MHZ TRELLIS CODEC CHIP FOR PARTIAL-RESPONSE CHANNELS
(1991-12-01)
SHUNG, CB
;
SIEGEL, PH
;
THAPAR, HK
;
KARABED, R
;
電子工程學系及電子研究所
We present a rate 8/10 matched-spectral-null (MSN) trellis codec chip which can increase noise tolerance in partial-response channels applicable to digital magnetic recording. The Viterbi detector in this codec features an area-efficient pipelined architecture and a modulo metric normalization technique. The chip was implemented in a 1.2-mu-m CMOS process with a die size of 22 mm2. It offers a 12-Mb/s data rate when operating at 30 MHz. Experimental results verified the predicted coding gain of 2.8 dB relative to the uncoded system at a bit-error rate of 10(-7).
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY
(1993-04-01)
SHUNG, CB
;
LIN, HD
;
CYPHER, R
;
SIEGEL, PH
;
THAPAR, HK
The Viterbi algorithm has been widely applied to many decoding and estimation applications in communications and signal processing. A state-parallel implementation is usually used in which one add-compare-select (ACS) unit is devoted to each state in the trellis. In this paper we present a systematic approach of partitioning, scheduling, and mapping the N trellis states to P ACS's, where N > P. The area saving of our architecture comes from the reduced number of both the ACS's and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the area-efficient architecture offers a favorable (smaller) area-time product, compared to a state-parallel implementation. These results will be demonstrated by application examples in the accompanying paper.
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
(1993-05-01)
SHUNG, CB
;
LIN, HD
;
CYPHER, R
;
SIEGEL, PH
;
THAPAR, HK
In the previous paper, we established the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm. In this paper, we will show area-efficient architectures for practical codes to illustrate the design procedures and demonstrate the favorable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes will be presented. We will also discuss the application of our area-efficient techniques to codes with a very large numbers of states, codes with time-varying trellises, and a programmable Viterbi decoder.
REAL-TIME RECORDING RESULTS FOR A TRELLIS-CODED PARTIAL-RESPONSE (TCPR) SYSTEM
(1993-11-01)
THAPAR, HK
;
SHUNG, CB
;
RAE, JW
;
KARABED, R
;
SIEGEL, PH
This paper describes the results of an experimental performance comparison between a Trellis-Coded Partial Response (TCPR) system and a Partial Response Maximum Likelihood (PRML) channel, using magneto-resistive (MR) recording heads and metal film disks. Measured data confirms that the TCPR method provides substantial performance advantage in terms of ontrack error rate, offtrack capability, and areal density.