Browsing by Author "Tai, Mao-Chou"

Now showing 1 - 9 of 9

A Dual-Gate InGaZnO4-Based Thin-Film Transistor for High-Sensitivity UV Detection
(2019-08-01)
Chen, Po-Hsun
;
Tsao, Yu-Ching
;
Chien, Yu-Chieh
;
Chiang, Hsiao-Cheng
;
Chen, Hua-Mao
UV-sensing devices have received significant recent attention for applications in areas such as human health, fire detection, and optical communication. One key factor for product commercialization is determining the optimal materials that allow for integration of excellent UV-sensing properties with compatibility with industrial fabrication processes. However, current UV sensors often fail to achieve this due to either mismatched materials or a device that must be excessively large in order to produce enough photocurrent for UV detection. The UV-light-sensing properties of an amorphous InGaZnO4 (IGZO) thin-film transistor with a dual-gate structure and relatively small device size (width/length = 50 mu m/10 mu m) that achieves high sensitivity through a threshold-voltage-(V-th)-adjustment method is proposed. Comparing the drain currents under UV exposure to those under darkened conditions indicates that the ratio between the photoinduced and dark current reaches 10(6). Furthermore, the UV sensitivity of the dual-gate transistors can be adjusted by varying the bottom gate voltage, with each pixel of the sensor then being read out separately via scan line pulses. This allows the dual-gate a-IGZO transistor to be used for high-performance UV sensing while being effectively integrated in display applications.
A Novel Structural Design Serving as a Stress Relief Layer for Flexible LTPS TFTs
(2019-01-01)
Wang, Yu-Xuan
;
Chang, Ting-Chang
;
Huang, Shin-Ping
;
Tai, Mao-Chou
;
Zheng, Yu-Zhe
In this work a novel device structure aiming to suppress the degradations under bending in flexible devices is demonstrated, named as a wing-shape TFT. Investigations of the electrical characteristics and reliabilities are supported by simulations, theoretical calculations, and structural discussions. First, through both electrical and mechanical stress simulation, the regions of degradation are confirmed to occur at the corner of the gate insulator. After long term mechanical stress, behaviors including an abnormal hump, serious threshold voltage (Vth) shifts, on-current increase, and off-current decrease are observed. By extending the active layer, also serving as a stress relief layer, removes the degradation regions away from the main channel. Therefore, the reliability of the devices is dramatically improved. The geometries of the wings in wing-shape TFTs are also in consideration. From results, with different wing lengths, a similar improvement of the reliability is shown, but the on current is enhanced when the wing length is extended. These phenomena are realized as a result of the difference in the effective width. The proposed wing-shape LTPS TFT has its potential and benefits for future flexible displays.
A Novel Structure to Reduce Degradation Under Mechanical Bending in Foldable Low Temperature Polysilicon TFTs Fabricated on Polyimide
(2020-05-01)
Wang, Yu-Xuan
;
Chang, Ting-Chang
;
Huang, Shin-Ping
;
Tai, Mao-Chou
;
Zheng, Yu-Zhe
In this study, a novel structural device, named as a wing-shaped TFT, is proposed and is demonstrated to prevent fast deterioration under mechanical bending in foldable devices. After long-term mechanical bending, standard low-temperature polysilicon TFTs exhibit instability behaviors such as sub-channel formation, serious threshold voltage shifts, an on-current (I-ON) increase, and an off-current (I-OFF) decrease. These phenomena are believed to be due to additional oxide traps along the channel-width edges of the gate insulator after bending. In order to suppress this degradation, a wing-shaped structure is proposed. By extending the active layer, degradation regions are shifted away from the main channel. Therefore, the reliability of the devices is enhanced. The transfer characteristics show enhanced electrical behavior after being held for 48 hours in a static bent condition, with an 88% drop in threshold voltage shift as well as a 55% decrease in subthreshold swing degradation, proving better durability of the foldable TFT to bending stress for devices with these wings. Time-dependent transfer characteristics, a COMSOL simulation, and device geometry are discussed to support our findings.
Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors
(2020-09-30)
Tu, Hong-Yi
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Tai, Mao-Chou
;
Tsai, Yu-Lin
Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.
Analysis of Negative Bias Temperature Instability Degradation in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors of Different Grain Sizes
(2019-11-01)
Tu, Hong-Yi
;
Tsao, Yu-Ching
;
Tai, Mao-Chou
;
Chang, Ting-Chang
;
Tsai, Yu-Lin
This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.
Effect of a-InGaZnO TFT Channel Thickness under Self-Heating Stress
(2019-09-18)
Tai, Mao-Chou
;
Chang, Po-Wen
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Tsai, Yu-Lin
In this work, indium-gallium-zinc-oxide thin film transistors (IGZO-TFTs) with different channel thicknesses were compared after self-heating stress (SHS). Although TFTs with a thicker channel have higher current during stress conditions, less degradation is reported. This degradation, manifest as the threshold voltage shift in the transfer characteristics, is well described by the stretched-exponential equation. In addition, the average effective barrier height, Et, is extracted to compare the difference in degradation between both TFTs, and finds that the barrier height in the thick channel device is twice that of the thin channel device. Finally, a COMSOL simulation is performed to demonstrate the electrical difference at the gate insulator layer and confirm such phenomena. (C) 2019 The Electrochemical Society.
Improvement of Resistive Switching Characteristics in Zinc Oxide-Based Resistive Random Access Memory by Ammoniation Annealing
(2020-03-01)
Wu, Pei-Yu
;
Zheng, Hao-Xuan
;
Shih, Chih-Cheng
;
Chang, Ting-Chang
;
Chen, Wei-Jang
In this experiment, the electrical performance of zinc oxide based-resistive random access memory (RRAM) is successfully improved by using annealing in ammonia hydroxide solution at low-temperature and high pressure to complete ammonium-doped ZnO based-RRAM. The results of material analysis indicate that using CO2 as ammonia hydroxide carrier during the annealing process leads to the reduction in dangling bond density. This can be clearly observed in the decrease in breakdown voltage during the forming process and a lower operating current during operation. Furthermore, in this ammonium-doped ZnO based-RRAM, we study the molecular doping of NH3 in ZnO, where the endurance and retention properties are improved as well. These improvements can be attributed to the higher concentration of nitrogen in the switching layer, which can effectively control the active oxygen ions during the operation process.
Improving Reliability of High-Performance Ultraviolet Sensor in a-InGaZnO Thin-Film Transistors
(2019-09-01)
Tsai, Yu-Lin
;
Chien, Yu-Chieh
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Tai, Mao-Chou
High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect I-ON/I-OFF ratio up to 10(6) and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies.
Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors
(2020-09-01)
Lin, Chih-Chih
;
Tai, Mao-Chou
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Wang, Yu-Xuan
In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.