Browsing by Author "Tai, YH"

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A distributed charge storage with GeO2 nanodots
(2004-04-05)
Chang, TC
;
Yan, ST
;
Hsu, CH
;
Tang, MT
;
Lee, JF
In this study, a distributed charge storage with GeO2 nanodots is demonstrated. The mean size and aerial density of the nanodots embedded in SiO2 are estimated to be about 5.5 nm and 4.3x10(11) cm(-2), respectively. The composition of the dots is also confirmed to be GeO2 by x-ray absorption near-edge structure analyses. A significant memory effect is observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window is estimated to similar to0.45 V. Also, a physical model is proposed to demonstrate the charge storage effect through the interfacial traps of GeO2 nanodots. (C) 2004 American Institute of Physics.
A source-follower type analog buffer using poly-Si TFTs with large design windows
(2005-11-01)
Tai, YH
;
Pai, CC
;
Chen, BT
;
Cheng, HC
;
電子工程學系及電子研究所
New simple source follower circuits using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) as analog buffers for the integrated data driver circuit of active-matrix liquid crystal displays and active-matrix light emitting diodes are discussed. In addition to the threshold voltage difference of driving TFTs, the unsaturated of output voltage arisen from the significant subthreshold current will also result in the difficulty of the buffer circuit design. The proposed circuit is capable of minimizing the variation from both the signal timing and the device characteristics.
Damage effect of fluorine implantation on PECVD alpha-SiOC barrier dielectric
(2005-08-01)
Yang, FM
;
Chang, TC
;
Liu, PT
;
Chen, CW
;
Tai, YH
in this work the dielectric properties of plasma enhanced chemical vapor deposited (PECVD) amorphous SiOC (alpha-SiOC) films with various concentrations of oxygen are investigated for the barrier dielectric application. Experimental results show after fluorine (F) ion implanted into alpha-SiOC film, the leakage current in carbide film is increased due to the generation of trap centers. Afterwards, the traps can be effectively repaired after thermal annealing, leading to the decrease of leakage current further. From the extraction of the current-voltage (J-E) characteristics, the conducting mechanism of the leakage current obeys the Poole-Frenkel type behavior for intrinsic, F-implanted and thermally annealed samples. Also, the barrier height of the F-implanted and thermally annealed samples are extracted and exhibits a higher value than that of the intrinsic sample. (c) 2005 Elsevier B.V. All rights reserved.
Degradation of capacitance-voltage characteristics induced by self-heating effect in poly-si TFTs
(2006)
Tai, YH
;
Huang, SC
;
Chiu, HL
;
光電工程學系
;
Department of Photonics
The degradation of poly-Si thin film transistors (TFTs) under self-heating stress was investigated via the capacitance between the source and the gate (C-GS), and that between the drain and the gate (C-GD). Consequently, the normalized C-GS and C-GD after stress positively shift 2 V for the gate voltage near flat band voltage. In addition, C-GS raises about 40% for the lower gate voltage, while C-GD raises only about 10%. With simulation results, it is found that the self-heating effect creates interface states near the source region and the deep states near drain, resulting in the different inclines of the of C-GS and C-GD curves.
Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels
(2005-10-01)
Wu, YC
;
Chang, TC
;
Liu, PT
;
Chen, CS
;
Tu, CH
This brief studies the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly doped drain (LDD) structures. The nanoscale TFT with ten 67-nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with each channel width decreasing, yielding a profile from a single-gate to tri-gate structure.
Effects of the rear interface states and fixed charges on the electrical characteristics of thin film transistors with thin amorphous silicon layers
(1996-06-01)
Tai, YH
;
Su, FC
;
Feng, MS
;
Cheng, HC
;
材料科學與工程學系
The electrical characteristics of the thin film transistors (TFT's) with hydrogenated amorphous silicon (a-Si:H) films thinner than 0.1 mu m have been carefully studied to show that the interface states and fixed charges at the rear interface will play the comparable effects to those at the front interface on the field effect conductance. It is dearly demonstrated that as the thickness of the active layer is smaller than the theoretically expected width of the space charge region, the potential at the rear interface will be affected by the gate voltage. This is very different from the conventional case with a thicker active layer. Since the TFT's at present have smaller typical thicknesses of the semiconductor films than the expected width of the space charge region, the effects of the interface states and the fixed charges at both the rear and front interfaces, as well as the bulk states of the thin a-Si:H films, must be taken into account concurrently.
Electrical properties of amorphous silicon films with different thicknesses in metal/insulator/semiconductor structures
(1996-05-01)
Tai, YH
;
Su, FC
;
Chang, WS
;
Feng, MS
;
Cheng, HC
The density of states (DOS) of hydrogenated amorphous silicon (a-Si:H) is an important issue in the study of the physics of amorphous semiconductors. In many earlier reports concerning the analysis of the field-effect conductance metal/insulator/ a-Si:H structures, namely, thin-film transistors (TFTs), the potential at the semiconductor surface apart from the gate insulator/a-Si:H interface, i.e., the rear interface, was assumed to be zero. However, in principle, as the thickness of the semiconductor film is smaller than the theoretically expected width of the space charge region, this assumption no longer holds. Hence, it is necessary to reconsider the band-bending phenomena of the a-Si:H active layers. It was found that the DOS, which was extracted previously from the field-effect conductance of the TFTs based on the assumption of the zero-potential rear interface, was appropriate only for the thick a-Si:H films. As for the thin semiconductor films, the accurate DOS can be obtained by fitting the calculated field-effect conductance, with a surmised possible DOS, to the experimentally measured data via the method developed.
Enhanced performance of poly-Si thin film transistors using fluorine ions implantation
(2005)
Tu, CH
;
Chang, TC
;
Liu, PT
;
Zan, HW
;
Tai, YH
Fluorine (F)-implanted polycrystalline silicon thin-film transistor (poly-Si TFT) are proposed for the enhancement of device performance. A significant improvement in electrical characteristics, such as I-ON/I-OFF ratio, and field effect mobility, can be realized in the new thin-film transistor. The field effect mobility for F-implanted poly-Si TFTs is 53.82 cm(2)/V-s, and higher than 19.74 cm(2)/V-s in conventional SPC poly-Si TFTs. Furthermore, the F-implanted poly- Si TFT exhibits high immunity against hot carrier effect and improved electrical reliability. The manufacturing processes are simple and without additional thermal annealing steps, thereby compatible with the conventional TFT fabrication processes. (c) 2005 The Electrochemical Society. All rights reserved.
High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels
(2004)
Wu, YC
;
Chang, CY
;
Chang, TC
;
Liu, PT
;
Chen, CS
We have investigated the lightly-doped drain (LDD) polysilicon thin-film transistors (poly-Si TFTs) with a series of multi-channel with different widths. The ten 67 nm-wide split channels TFT has best gate control due to its tri-gate structure, and has lowest poly-Si grain boundary defects, which were passivated by NH3 plasma effectively due to its split nano-wires structure. The proposed TFT exhibits high performance electrical characteristics, such as a high ON/OFF current ratio (>10(9)), a steep subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL), suppressed kink-effect, and superior reliability.
High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure
(2004-05-10)
Wu, YC
;
Chang, TC
;
Chang, CY
;
Chen, CS
;
Tu, CH
This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient NH3 plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio (>10(8)), a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies. (C) 2004 American Institute of Physics.
Improvement of reliability for polycrystalline thin-film transistors using self-aligned fluorinated silica glass spacers
(2005)
Tu, CH
;
Chang, TC
;
Liu, PT
;
Zan, HW
;
Tai, YH
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with self-aligned fluorine-doped SiO2 (FSG) spacer were investigated in this study. The presence of FSG spacers can effectively reduce the lateral electrical field near the drain side of a poly-Si TFT device, and strongly passivate Si dangling bonds at the grain boundaries. The significant enhancement in electrical performance suppresses serious kink effect and improves electrical reliability of poly-Si TFTs effectively. In addition, the proposed poly-TFT structure is uncomplicated and compatible with existing TFT manufacturing processes. (c) 2005 The Electrochemical Society.
New pixel circuits for driving active matrix organic light emitting diodes
(2006-02-01)
Chen, BT
;
Tai, YH
;
Kuo, YJ
;
Tsai, CC
;
Cheng, HC
New pixel circuit designs for active matrix organic light emitting diodes (AMOLEDs), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) were proposed and verified by SPICE simulation and fabrication results. Threshold voltage compensation pixel circuits consisting of five TFTs, one additional control signal, and one storage capacitor were used to enhance display image uniformity. The simulation and measured results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics. (c) 2006 Elsevier Ltd. All rights reserved.
Process-related instability mechanisms for the hydrogenated amorphous silicon thin film transistors
(1995)
Tai, YH
;
Su, FC
;
Feng, MS
;
Cheng, HC
;
電子工程學系及電子研究所
Reducing threshold voltage shifts in amorphous silicon thin film transistors by hydrogenating the gate nitride prior to amorphous silicon deposition
(1997-09-01)
Tsai, JW
;
Huang, CY
;
Tai, YH
;
Cheng, HC
;
Su, FC
A short H-2 plasma treatment of the gate SiNx before depositing amorphous silicon (a-Si:H) is found to significantly decrease the threshold shifts in the bias stress, inverted a-Si:H thin film transistors (TFTs). The reduced threshold voltage shift is attributed to a plasma induced reconstruction of SiNx precursors leading to the removal of the weak bonds. A prolonged plasma treatment, however, degraded the TFT characteristics; this was traced H-2 plasma damage which eventually generated a rough a-Si:H/SiNx interface. (C) 1997 American Institute of Physics.
Reducing threshold voltage shifts in amorphous silicon thin film transistors by hydrogenating the gate nitride prior to amorphous silicon deposition
(1997-09-01)
Tsai, JW
;
Huang, CY
;
Tai, YH
;
Cheng, HC
;
Su, FC
A short H-2 plasma treatment of the gate SiNx before depositing amorphous silicon (a-Si:H) is found to significantly decrease the threshold shifts in the bias stress, inverted a-Si:H thin film transistors (TFTs). The reduced threshold voltage shift is attributed to a plasma induced reconstruction of SiNx precursors leading to the removal of the weak bonds. A prolonged plasma treatment, however, degraded the TFT characteristics; this was traced H-2 plasma damage which eventually generated a rough a-Si:H/SiNx interface. (C) 1997 American Institute of Physics.
Statistical study on the temperature dependence of the turn-on characteristics for p-type LTPS TFTs
(2005)
Tai, YH
;
Kuo, YF
;
光電工程學系
;
Department of Photonics