Browsing by Author "Tang, Cheng-Hao"

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A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
(2007)
Wong, Cheng-Chi
;
Tang, Cheng-Hao
;
Lai, Ming-Wei
;
Zheng, Yan-Xiu
;
Lin, Chien-Ching
This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate.