Browsing by Author "Tang, Denny D."

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Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs
(2006-06-01)
Chan, Chien-Tai
;
Tang, Chun-Jung
;
Wang, Tahui
;
Wang, Howard C. -H.
;
Tang, Denny D.
Drain current degradation in HfSiON gate, dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.
Discrete dopant fluctuated 20nm/15nm-gate planar CMOS
(2007)
Yang, Fu-Liang
;
Hwang, Jiunn-Ren
;
Chen, Hung-Ming
;
Shen, Jeng-Jung
;
Yu, Shao-Ming
We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V-t standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V-t variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.