Browsing by Author "Tang, H"

Now showing 1 - 4 of 4

Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process
(2001)
Ker, MD
;
Lo, WY
;
Chen, TY
;
Tang, H
;
Chen, SS
An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-mum shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.
Electrostatic discharge protection under pad design for copper-low-K VLSI circuits
(2004-04-01)
Lee, JW
;
Li, YM
;
Chao, A
;
Tang, H
;
友訊交大聯合研發中心
An electrostatic discharge (ESD) under pad structure is proposed and demonstrated for the novel copper-low-K circuit design. By using this approach, the density of both devices and pads could be markedly improved; in a rough estimation, approximately five to twenty percent of the chip area could be saved. Moreover, tests of ESD, latch-up, and bond yield are performed and are found to be better than those of the conventional ones. The designed structure could be considered as a very effective achievement, and this is particularly true for the sub-0.1 mu m circuit with copper-low-K interconnections.
Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology
(2001)
Ker, MD
;
Hong, KK
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Chen, TY
;
Tang, H
;
Huang, SC
Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-mum partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.
Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology
(1998)
Ker, MD
;
Chen, TY
;
Wu, CY
;
Tang, H
;
Su, KC
A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 Angstrom) of the input stage in a 0.25-mu m CMOS technology and sustain an ESD level above 2000V without extra process modification.