Browsing by Author "Tang, Kai-Neng"

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Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection
(2015)
Liao, Seian-Feng
;
Tang, Kai-Neng
;
Ker, Ming-Dou
;
Yeh, Jia-Rong
;
Chiou, Hwa-Chyi
Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-mu m HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.
Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity
(2015)
Tang, Kai-Neng
;
Liao, Seian-Feng
;
Ker, Ming-Dou
;
Chiou, Hwa-Chyi
;
Huang, Yeh-Jen
Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-mu m BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.