Browsing by Author "Tang, Ying-Tsan"

Now showing 1 - 6 of 6

A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Bias-dependent bandwidth of the conductance in the presence of electron-phonon interaction
(2010-04-01)
Tang, Ying-Tsan
;
Lin, Kao-Chin
;
Chuu, Der-San
;
電子物理學系
;
Department of Electrophysics
We study the electronic transport in the presence of electron-phonon interaction (EPI) for a molecular electronic device. Instead of mean field approximation (MFA), the related phonon correlation function is conducted with the Langreth theorem (LT). We present formal expressions for the bandwidth of the electron's spectral function in the central region of the devices, such as quantum dot (QD), or single molecular transistor (SMT). Our results show that the out-tunneling rate depends on the energy, bias voltage and the phonon field. Besides, the predicted conductance map, behaving as a function of bias voltage and the gate voltage, gets blurred at the high bias voltage region. These EPI effects are consistent with the experimental observations in the EPI transport experiment. (C) 2010 Elsevier Ltd. All rights reserved.
Influence of phonon-associated tunneling rate on transport through a single-molecule transistor
(2011-01-01)
Tang, Ying-Tsan
;
Chuu, Der-San
;
Lin, Kao-Chin
;
電子物理學系
;
Department of Electrophysics
We study the electronic transport through a single-molecule transistor (SMT) by considering the phonon-associated tunneling rate We find that the electron-phonon interaction (EPI) changes the constant conductivities of the leads into a multi-channel structure of single vibration frequency This interference of the multi-channel tunneling process results in a bias-dependent tunneling rate and obscures the conductance peaks at large bias voltage The bias-dependent tunneling rate further causes a remarkable conductivity gap between the chemical potential of the leads (n = 0) and the first phonon sideband (n = 1) These anomalies are consistent with the experimental observations in transport experiments (C) 2010 Elsevier Ltd All rights reserved
Investigation of strain-induced phase transformation in ferroelectric transistor using metal-nitride gate electrode
(2017-03-01)
Chiu, Yu-Chien
;
Cheng, Chun-Hu
;
Chang, Chun-Yen
;
Tang, Ying-Tsan
;
Chen, Min-Cheng
In this work, we report a ferroelectric memory with strainedgate engineering. The memory window of the high strain case was improved by similar to 71% at the same ferroelectric thickness. The orthorhombic phase transition (from ferroelectric to antiferroelectric transition) plays a key role in realizing negative capacitance effect at high gate electric field. Based on a reliable first principles calculation, we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. This ferroelectric strain technology shows the potential for emerging device application.
One-Transistor Ferroelectric Versatile Memory: Strained-Gate Engineering for Realizing Energy-Efficient Switching and Fast Negative-Capacitance Operation
(2016)
Chiu, Yu-Chien
;
Cheng, Chun-Hu
;
Chang, Chun-Yen
;
Tang, Ying-Tsan
;
Chen, Min-Cheng
In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by similar to 47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over similar to 4 decade of I-D to provide a 1 similar to 10 fA/mu m I-off and >10(8) I-on/I-off ratio, which allows for a fast 20-ns P/E switching during 10(12) cycling endurance.
Self-organized Pairs of Ge Double Quantum Dots with Tunable Sizes and Spacings Enable Room-Temperature Operation of Qubit and Single-Electron Devices
(2019-01-01)
Peng, Kang-Ping
;
Chen, Ching-Lun
;
Tang, Ying-Tsan
;
Kuo, David
;
George, Thomas
We report the first-of-its-kind, paired Ge double quantum dots (DQDs) using spacer technology in combination with selective oxidation of Si0 85Ge0 15 in a self-organization approach. Process-controlled tunability of the spherical Ge QD diameters (5-20nm) and inter-QD spacings as close as 12nm were achieved by thermal oxidation of poly-SiGe spacer islands at each sidewall corner of Si3N4/poly-Si ridges. Based on the capability of producing highly-symmetrical Ge DQDs in terms of QD sizes and the coupling barriers of thermal SiO2/densified Si3N4 between the QDs and proximal electrodes, we demonstrated room-temperature operation of Ge qubit devices, within which one QD encodes charges and the other QD-single-electron transistor (SET) senses and read-out the qubit. Theoretical analysis on the size-tunable density of states for Ge QDs and the tunneling paths in DQDs were conducted. Our Ge DQD system enables a practically achievable building block for QD qubit devices on Si platform.