Browsing by Author "Tao, H. J."

Now showing 1 - 6 of 6

HfSiON n-MOSFETs using low-work function HfSi chi gate
(2006-09-01)
Wu, C. H.
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Hung, B. F.
;
Chin, Albert
;
Wang, S. J.
;
Yen, F. Y.
The authors have developed a novel high-temperature stable HfSix gate for high-kappa HfSiON gate dielectric. After a 1000 degrees C RTA, the HfSix/HfSiON devices showed an effective work function of 4.27 eV and a peak electron mobility of 216 cm(2)/V (.) s at 1.6-nm equivalent oxide thickness, with additional merit of a process compatible with current very large scale integration fabrication lines.
High temperature stable [Ir3Si-TaN]/HfLaON CMOS with large work-function difference
(2006)
Wu, C. H.
;
Hung, B. F.
;
Chin, Albert
;
Wang, S. J.
;
Chen, W. J.
We report novel 1000 degrees C-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good phi(m.eff) of 5.08 and 4.24 eV, low V, of -0.10 and 0.18 V, high mobility of 84 and 217 cm(2)/Vs at 1.6 nm EOT, and small 850 degrees C BTI < 20 mV (10 MV/cm for 1 hr) are measured.
High-temperature stable HfLaON p-MOSFETs with high-work-function Ir3Si gate
(2007-04-01)
Wu, C. H.
;
Hung, B. F.
;
Chin, Albert
;
Wang, S. J.
;
Wang, X. P.
We report a novel 1000 degrees C stable HfLaON p-MOSFET with Ir3Si gate. Low leakage current of 1.8 x 10(-5) A/cm(2) at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm(2)/V center dot s are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degrees C rapid thermal annealing is fully compatible to current very large scale integration fabrication lines.
High-temperature stable IrxSi gates with high work function on HfSiON p-MOSFETs
(2007-02-01)
Hung, B. F.
;
Wu, C. H.
;
Chin, Albert
;
Wang, S. J.
;
Yen, F. Y.
A novel 1000 degrees C-stable IrxSi gate on HfSiON is shown for the first time with full process compatibility to current very-large-scale-integration fabrication lines and proper effective work function of 4.95 eV at 1.6-nm equivalent-oxide thickness. In addition, small threshold voltages and good hole mobilities are measured in IrxSi/HfSiON transistors. The 1000 degrees C thermal stability above pure metal (900 degrees C only) is due to the inserted 5-nm amorphous Si, which also gives less Fermi-level pinning by the accumulated metallic full silicidation at the interface.
Modeling of nitrogen profile effects on direct tunneling probability in ultrathin nitrided oxides
(2008-01-14)
Liu, Po-Tsun
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Huang, Chen-Shuo
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Lee, D. Y.
;
Lim, P. S.
;
Lin, S. W.
The dependence of the gate tunneling current (J(g)) on nitrogen profile (N profile) within an ultrathin silicon oxynitride film is reported. It was found that gate tunneling current is dependent on N profile, even with equal oxide thickness and nitrogen dosage. Gate tunneling current increased with steeper N profile, and it had higher sensitivity for p-type metal-oxide-semiconductor field-effect transistor (MOSFET) than n-type MOSFET. A direct tunneling model based on Wentzel-Kramers-Brillouin approximation has been proposed. The model described the influence of N profiles on gate tunneling current through local change of dielectric constant, band bending, and effective mass. Also, it reasonably explained the different J(g) sensitivity in n-/p-MOSFETs, a phenomenon that has not been addressed in earlier publications. (c) 2008 American Institute of Physics.
Novel Silicon Surface Pre-Treatment (SSPT) technique for CMOS device performance boosting
(2008-01-01)
Lee, Da-Yuan
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Chen, C. C.
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Huang, C. H.
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Lim, P. S.
;
Chan, M. H.
In this paper, a novel surface treatment technique using Silicon Surface Pre-Treatment (SSPT) technique to boost high performance CMOS circuit is reported. This approach provides a smooth silicon surface and extends the effective channel width to enhance device performance on both N and PMOSFET. In this work, a smooth and rounded active area (AA) surface was successfully fabricated. Using this technique, we demonstrated a significant device boost of 15% and 7% on small dimension N and PMOSFET, respectively. These achievements were demonstrated without negative impact on GOI and NBTI.