Browsing by Author "Tao, HJ"

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Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO(2) high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO(2) high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO(2) high-k gate stacks.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO2 high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.
HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicide
(2006-06-01)
Wu, CH
;
Hung, BF
;
Chin, A
;
Wang, SJ
;
Yen, FY
The authors have fabricated low-temperature fully silicided YbSi2-x-gated n-MOSFETs that used an HfAION gate dielectric with a 1.7-nm EOT. After a 600 degrees C rapid thermal annealing, these devices displayed an effective work function of 4.1 eV and a peak electron mobility of 180 cm(2)/V(.)s. They have additional merit of a process compatible with current very large scale integration fabrication lines.
Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide
(2006-05-01)
Wu, WH
;
Tsui, BY
;
Huang, YP
;
Hsieh, FC
;
Chen, MC
A new circuit model of -five elements has been proposed for the two-frequency capacitance-voltage (C-V) correction of high-k gate dielectric and ultrathin oxide. This five-element circuit model considered the static and dynamic dielectric losses in a lossy MOS capacitor, the parasitic well/substrate resistance, and the series inductance in the cables and probing system. Each of the circuit elements could be easily extracted from the two-frequency C-V and static current-voltage (I-V) measurements if some criteria are well satisfied. In addition, this model can also be transformed into another two four-element circuit models to simplify the analysis and calculations, depending on the gate ea age current.