Browsing by Author "Tao, Hun-Jan"

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Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET
(2008-11-01)
Liu, Po-Tsun
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Huang, Chen-Shuo
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Lim, Peng-Soon
;
Lee, Da-Yuan
;
Tsao, Shueh-Wen
Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.
Spatial and energetic distribution of border traps in the dual-layer HfO2/SiO2 high-k gate stack by low-frequency capacitance-voltage measurement
(2006-10-16)
Wu, Wei-Hao
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Tsui, Bing-Yue
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Chen, Mao-Chieh
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Hou, Yong-Tian
;
Jin, Yin
Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2/SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.
Transient charging and discharging behaviors of border traps in the dual-layer HfO2/SiO2 high-k gate stack observed by using low-frequency charge pumping method
(2007-06-01)
Wu, Wei-Hao
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Tsui, Bing-Yue
;
Chen, Mao-Chieh
;
Hou, Yong-Tian
;
Jin, Yin
Transient charging and discharging of border traps in the dual-layer HfO2/SiO2 high-kappa. gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO2 high-kappa. dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10(-8)-10(-4) s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling.
Two-dimensional dopant profiling by electrostatic force microscopy using carbon nanotube modified cantilevers
(2008-08-13)
Chin, Shu-Cheng
;
Chang, Yuan-Chih
;
Hsu, Chen-Chih
;
Lin, Wei-Hsiang
;
Wu, Chih-I
A two-dimensional (2D) dopant profiling technique is demonstrated in this work. We apply a unique cantilever probe in electrostatic force microscopy (EFM) modified by the attachment of a multiwalled carbon nanotube (MWNT). Furthermore, the tip apex of the MWNT was trimmed to the sharpness of a single-walled carbon nanotube (SWNT). This ultra-sharp MWNT tip helps us to resolve dopant features to within 10 nm in air, which approaches the resolution achieved by ultra-high vacuum scanning tunnelling microscopy (UHV STM). In this study, the CNT-probed EFM is used to profile 2D buried dopant distribution under a nano-scale device structure and shows the feasibility of device characterization for sub-45 nm complementary metal-oxide-semiconductor (CMOS) field-effect transistors.