Browsing by Author "Ting, Yi-Ching"

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A QFHD 30-frames/s HEVC Decoder Design
(2016-04)
Chiang, Pai-Tse
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Ting, Yi-Ching
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Chen, Hsuan-Ku
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Jou, Shiau-Yu
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Chen, I-Wen
The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variable-size coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the 64x64 block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by 16 x 16 block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a 4x4 block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported 4096x2160
Fast Intra Prediction Algorithm with Transform Domain Edge Detection For HEVC
(2012)
Ting, Yi-Ching
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To solve the high computational demand of intra prediction in the latest HEVC (High Efficiency Video Coding) standard, this paper proposes a fast intra prediction algorithm with three step mode selection and the transform domain edge detection. The simulation results show that the proposed algorithm can save 44.2% encoding time in average for all-intra High Efficiency case compared to the default encoding scheme in HM-6.0rc1, with slightly 2.8% BD-rate increases.
Gradient-Based PU Size Selection For HEVC Intra Prediction
(2014-01-01)
Ting, Yi-Ching
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a fast hardware friendly intra block size selection algorithm with simple gradient calculations and the bottom-up structure to solve the high computational demand of intra prediction in the latest HEVC (High Efficiency Video Coding) standard. The simulation results show that the proposed algorithm can save 57.3% encoding time in average for all-intra main case compared to the default encoding scheme in HM-9.0rc1, with slightly 2.2% BD-rate increases.