Browsing by Author "Tsai, C. H."

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A Full-Color, White Light Emission of Quantum-Dot-Based Display Technology Using Pulsed Spray Method with Distributed Bragg Reflector
(2012)
Chen, K. J.
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Chen, H. C.
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Lin, C. C.
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Tsai, H. H.
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Tsai, K. A.
A colloidal quantum dot light-emitting multi-layer structure with HFO2/SiO2 distributed Bragg reflector is manufactured by pulse spray method. A pure white light with strong enhancement due to better utilization of UV pump was demonstrated. (C)2012 Optical Society of America
A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime
(2009)
Hsieh, E. R.
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Chung, Steve S.
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Liu, P. W.
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Chiang, W. T.
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Tsai, C. H.
A new yet simple approach, V(D,sat) method, without complicate temperature measurement setup, has been developed to investigate the carrier transport characteristics for MOSFET devices in the quasi-ballistic regime. It has shown quite good matches with that of Temperature Dependent Method (TDM) developed from the quantum theory [1]. For the first time, the carrier transport properties after HC stress were also examined based on the proposed method. Moreover, method has been applied to examine the carrier transport and reliabilities in advanced strain-CMOS devices. In terms of the device performance, the enhancement of the drain current is strongly related to the transport parameter, the injection velocity, V(inj) which serves as a good monitor for the strain design and current enhancement. While, considering the device reliability after the HC stress, ballistic efficiency, B(sat) is responsible for the I(D) degradation as a result of the increase in interface scatterings. Finally, a roadmap of the V(inj) from those reported results has been provided which serves as a good reference for designing high performance strain-based CMOS devices.
A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement
(2009)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I(D)-RTN (Drain Current Random Telegraph Noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL, also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
(2009)
Chung, Steve S.
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Hsieh, E. R.
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Liu, P. W.
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Chiang, W. T.
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Tsai, S. H.
A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I(D.sat) current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%-1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover. PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
Methods of determining the contact between a probe and a surface under scanning electron microscopy
(2006-10-01)
Nien, C. -H.
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Tsai, C. H.
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Shin, K. Y.
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Jian, W. B.
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電子物理學系
Based on the charging effect common to various kinds of electron microscopy, we have developed novel methods of determining "when" and "where" a probe starts to contact an electrically isolated surface. The touchdown of an electrically grounded probe leads to an acute change in the imaging contrast of the contacted surface, which also causes a rapid jump (ranging from a few to tens of picoamperes) of the grounding current. Thus, the detection of contact can be carried out in both qualitative and quantitative manners, providing a basis for establishing relevant standard procedures. In addition, we have achieved the spatial mapping of the contact point(s) using a specially designed lithographical pattern with two mutually vertical sets of parallel conductive lines. The precision of this mapping technique is simply determined by the pitch of parallel lines, which can be as small as the capability achievable in e-beam lithography. A possible "one-probe" version of the electrical characterization is also discussed with the same underlying principle, which may turn out to be indispensable for various studies and applications of nanostructures. Further development along this track is promising to realize an instrumentally simple version of "scanning electronspectroscopy" with various modes. (c) 2006 American Institute of Physics.
More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable Reliability
(2008)
Chung, Steve S.
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Hsieh, E. R.
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Huang, D. C.
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Lai, C. S.
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Tsai, C. H.
In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
National Project on 45 to 32 nm Metal Oxide Semiconductor Field Effect Transistors for Next Century IC Fabrications
(2008)
Hwang, Huey-liang
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Wang, C. W.
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Chang, K. H.
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Tsai, C. H.
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Leou, K. C.
It is well known that the Taiwan Semiconductor industries play the very key roles for the worldwide IC foundry, and the advanced research of nanoelectronics is the lifeline for its long term developments. Professor Huey-liang Hwang effectively integrated the most outstanding research team and resource in Taiwan on the National Project on Nanometer CMOS Transistors for the 21 century, which is sponsored by the Ministry of Economic Affairs of ROC. A dozen of Professors from NTHU( National Tsing Hua University) with expertise at the novel materials and analysis and NCTU( National Chiao Tung University) with expertise at devices and reliability are devoted to the studies and are in collaboration with the world-wide-known company such as TSMC, and breakthrough of the key technologies of 45-32 nm technologies are achieved. The objective of this project is focused on the development of advanced metal gate/high-k MOSFET for 45 nm node generation and beyond, the efforts include the world first successful suppression the oxide/Si interfacial layer formation by using a bi-layer composite of HfO2 3.2 nm (ALD)/HfO2 1.5 nm (MBE), the results show a dielectric constant of 16 and an EOT of 1.15 nm, a Dit was estimated to be 4.6x10(11)cm(-2)eV(-1) with the leakage at Vfb-1V being 8.5x10(-6) A/cm(2). Also, the thermal stability of HfO2, HfAlOx alloy and Al2O3/HfO2 stack, prepared by ALD were compared, the incorporation of Al in alloy form gave superior characteristics by retaining an amorphous structure up to 1000 C, which suppress the leakage current and retards growth of the interfacial layer giving the least increment of EOT and interface traps. Besides, by incorporating Al into TiO2 gave an EOT value of the Al2O3/TiAlOx/Al2O3 film down to 0.8 nm. Furthermore, high selectivity was obtained via etching the HfAlO and silicon wafer with pattern using the ICP Plasma. In this project, YbSi metal gate for n-MOSFET and IrSi metal gate p-MOSFET were successfully fabricated for the HfAlON MESFET. The results showed the good effective workfunction of 4.15 and 4.9 eV and no degradation of gate dielectric current and mobility in the YbxSi/HfAlON and IrxSi/HfAlON FUSI-gates by reducing the metal diffusion at lower temperatures.
New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyond
(2008)
Hsieh, E. R.
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Chung, Steve S.
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Lin, Y. H.
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Tsai, C. H.
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Liu, P. W.
In this work, for the first time, an abnormal leakage current has been observed in MOSFET with 50nm channel length and beyond. This effect shows that, in an ultra-short channel MOSFET, sub-threshold swing (SS) and I(off) are decreased for back-biased nMOSFET and pMOSFET. This effect is attributed to the BJT-induced current from the source to the drain. An experimental approach has been used to verify the existence of this BJT current component. As a consequence, this BIT current can be reduced with appropriate control of the S/D-to-substrate junction. As an application of the approach to advanced embedded-SiC MOSFET with various splits, it was found that a higher band-offset of S/D-to-substrate junction will give rise to a larger the BJT ballistic transport current. This provides us important information on reducing the leakage current for advanced CMOS with 50nm and beyond.
New Observations on the Physical Mechanism of Vth-Variation in Nanoscale CMOS Devices After Long Term Stress
(2011)
Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Huang, R. M.
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Tsai, C. T.
A new effect, called random trap fluctuation(RTF), is proposed to study the impact of hot carrier stress on the device variability. It was found that not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or FN-stress, induce the V(th) variation. After the FN stress, it was found that Vth variation is worse in pMOSFETs due to stress-induced interface traps. While, under the HC stress, different Vth variations were found for nMOSFETs and pMOSFETs. The Vth variation is enhanced in pMOSFETs due to RTF and reduced in nMOSFET as a result of the Trap Blocking Effect (TBE). RTF in pMOSFET might be the dominant factor of CMOS reliability for future generations.
New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI Reliabilities for 65nm node CMOS devices and beyond
(2006)
Chung, Steve S.
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Huang, D. C.
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Tsai, Y. J.
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Lai, C. S.
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Tsai, C. H.
In this paper, new observations on the uniaxial and biaxial strain-induced hot carrier reliability and/or NBTI in nMOSFET and pMOSFET respectively have been reported for the first time. Uniaxial and biaxial strained nMOSFET and pMOSFET have been extensively examined. Different mechanisms are responsible for different strains in nMOSFET and pMOSFET. For the nMOFETs, it was found that uniaxial strain device has comparable HC reliability with the control device, while biaxial SiGe-strained device exhibits a much worse reliability. This is related to a large impact ionization rate in a biaxial strain which leads to a much worse reliability. For the pMOSFETs, either uniaxial or biaxial strained device shows a comparable amount of HC degradation, while SiGe S/D strained structure might be better considering process complexity, performance, and reliability Although NBTI is still a great concern in SiGe S/D devices, embedded SiGe S/D technique can improve greatly the device NBTI reliability. These results provide a valuable guideline for the present 65nm and beyond CMOS device design with focus on the strain engineering.
Optimal design of ITO/organic photonic crystals in polymer light-emitting diodes with sidewall reflectors for high efficiency
(2012-09-01)
Tsai, C. H.
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Chao, Paul C. -P.
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影像與生醫光電研究所
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電機工程學系
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Institute of Imaging and Biomedical Photonics
This study aims to achieve large extraction of light emission from polymer light emitting diodes (PLEDs) via optimizing photonic crystals (PCs) and sidewall angle reflectors. Both PCs and sidewall reflectors can be resulting in increasing light emission in useful directions and reducing refection loss. The optimization is achieved through the optical modeling using a 3D finite-difference time-domain (FDTD) method and the intelligent numerical optimization technique, genetic algorithm (GA). The optimal design of PCs and sidewall angle reflectors are presented in details. To accurately predict light extraction of the PLED, the numerical simulation tool, the FDTD method is employed. Based on the FDTD simulation, the optimal sidewall angle which can increase maximum light extraction efficiency (LEE) in our designed PLED structure is 35A degrees. With the optical modeling of optimal sidewall angle reflectors via FDTD computation and the next step is using GA optimization to seek optimal pitch and radius of photonic crystals. According to the GA optimal result, the ratio of pitch to wavelength is 0.47 times and the ratio of radius to pitch is 0.25 times. GA is a powerful tool to cope with a complicated optimization problem with multiple variables to optimize. The PLEDs with optimized PCs and angle of sidewall reflectors would increase extraction of light emission from 20 to 26 % and the 3D FDTD calculation was conducted to explain this result.
Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC Applications
(2012-10-01)
Yang, C. L.
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Tsai, C. H.
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Li, C. I.
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Tzeng, C. Y.
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Lin, G. P.
In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.
Technology roadmaps on the ballistic transport in strain engineered nanoscale CMOS devices
(2007)
Chung, Steve S.
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Tsai, Y. J.
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Tsai, C. H.
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Liu, P. W.
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Lin, Y. H.
As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the ION current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100nm regime.
The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology
(2008)
Hsieh, E. R.
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Chang, Derrick W.
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Chung, S. S.
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Lin, Y. H.
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Tsai, C. H.
In this paper, the device performance in terms of its transport charactertitics and reliability of the MOS devices on the SOI and strained-SOI have been examined. For the first time, both the transport and reliability characteristics have been established from. experimental SOI and SSOI nMOSFETs. It was characterized by two parameters, the ballistic efficiency and the injection velocity. Experimental verifications on rMOSFETs with both technologies with tensile-stress enhancement have been made. For SSOI devices, it shows the expected drain current enhancements. For the reliability evaluations, SOI shows a smaller lattice such that it exhibits a much worse hot carrier (HC) reliability, while SSOI device shows a poorer interface quality verified from the FN-stress experiment. In general, although SSOI exhibits a worse interface quality while its reliability is much better than that of SOI's. Moreover, SSOI device shows a very high injection velocity as a result of the high strain of the device which makes it successful for drain current enhancement.
The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientations
(2007)
Tsai, Y. J.
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Chung, Steve S.
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Liu, P. W.
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Tsai, C. H.
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Lin, Y. H.
The channel backscattering and injection velocity of carriers in advanced CMOS devices are the two key parameters for achieving high drain current enhancement. For the first time, an extensive study of these transport parameters for different substrate orientations has been evaluated for both nMOSFET and pMOSFET. By suitably choosing the substrate orientation, it may achieve a reduced backscattering and an increased injection velocity, which is preferable for designing high performance logic CMOS devices. Results show that, in pMOSFET, (110) substrate is preferred and current enhancement can be greatly enhanced in the < 112 > channel. In comparison, (110) substrate in nMOSFET has an adverse effect in reducing driving current as a result of poorer transport characteristics. Therefore, (100) substrate is expected for nMOSFET design. A guideline is then summarized for the optimum design of high performance CMOS devices.
The improvement of catalytic efficiency by optimizing Pt on carbon cloth as a cathode of a microbial fuel cell
(2013-10-01)
Yen, S. J.
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Tsai, M. C.
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Wang, Z. C.
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Peng, H. L.
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Tsai, C. H.
This paper presents the performance of Pt deposited by different deposition methods, including electrodeposition, e-gun, and sputtering on a carbon cloth as a cathode in a microbial fuel cell (MFC) system. The results indicate that Pt deposited by electrodeposition exhibits the highest active efficiency on hydrogen electroabsorption. According to XPS fitting results, the amount of Pt (0), zero-valent Pt, existing in Pt deposited on carbon cloth by electrodeposition was larger than that in Pt deposited by e-gun and sputtering. The cyclic voltammogram analyses also show more real active surface area of Pt deposited by electrodeposition, mostly contributed by its smaller particle size/shape and higher catalytic effect. Besides, the total impedance of Pt deposited by electrodeposition was lower than that of Pt deposited by e-gun and sputtering from EIS measurement at 0.1 Hz. Applied to MFC system, the highest power density was manifested and the least Pt loading were observed for the Pt deposited on carbon cloth by electrodeposition. It is therefore can be concluded that the electrodeposited-Pt exhibit superior performance as a cathode for future MFC applications. (C) 2013 Elsevier Ltd. All rights reserved.
The Understanding of Multi-level RTN in Trigate MOSFETs Through the 2D Profiling of Traps and Its Impact on SRAM Performance: A New Failure Mechanism Found
(2012)
Hsieh, E. R.
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Tsai, Y. L.
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Chung, Steve S.
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Tsai, C. H.
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Huang, R. M.
The impact of multi-level RTN on SRAM cells bas been experimentally demonstrated on both planar and trigate CMOS devices. First, to study multi-level RTN, a simple experimental method has been developed to take the 2D profiling of multi-traps in both oxide depth (vertical) and channel(lateral) directions in the gate oxide. Then, the role of traps in the switching mechanisms of SRAM cells has also been examined. Results show that the multi-traps will degrade RSNM (read static noise margin), as well as cause transition failure in SRAM operations. This is the first being observed and reported that will be considered as a major criterion in the future low voltage design of SRAM cells.
The Understanding of Strain-Induced Device Degradation in Advanced MOSFETs with Process-Induced Strain Technology of 65nm Node and Beyond
(2010)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the origin of the strained-induced degradation in the MOSFETs with process-induced strain has been investigated by the ID-RTN ( Drain Current Random Telegraph Noise) technique. The process-induced strain on devices will make worse the device reliability, as reported in [1-2]. First, the ID-RTN has been employed to study the reliability of two different types of strain devices, i.e., the CESL strain and SiC S/D strain on nMOSFETs. Both CESL and SiC S/D nMOSFETs exhibit poorer reliability compared to bulk devices. However, their impacts to the much worse degradation are different. Results demonstrated that, for the strain in CESL device, it introduced extra mobility scattering in the vertical direction, while in SiC S/D device, the tensile strain along the channel causes an increase of trap generation via the horizontal field only. The CESL process introduces an additional compressive strain vertical to the channel such that it shows much worse reliability than the SiC S/D ones.
The Understanding of the Bulk Trigate MOSFET's Reliability Through the Manipulation of RTN Traps
(2013)
Hsieh, E. R.
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Wu, P. C.
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Chung, Steve S.
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Tsai, C. H.
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Huang, R. M.
The manipulation of RTN-trap profiling bas been experimentally demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. This is the first being reported that the positions of RTN-traps can be manipulated, showing significant advances for the understanding of the trap generation and the impact on the device reliability. Results have demonstrated why trigate exhibits much worse reliability than the planar ones.