Browsing by Author "Tsai, C. T."

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A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
(2014)
Hsieh, E. R.
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Hung, C. M.
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Wang, T. Y.
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Chung, Steve S.
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Huang, R. M.
Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, A(vt), A(gm), in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.
A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime
(2009)
Hsieh, E. R.
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Chung, Steve S.
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Liu, P. W.
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Chiang, W. T.
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Tsai, C. H.
A new yet simple approach, V(D,sat) method, without complicate temperature measurement setup, has been developed to investigate the carrier transport characteristics for MOSFET devices in the quasi-ballistic regime. It has shown quite good matches with that of Temperature Dependent Method (TDM) developed from the quantum theory [1]. For the first time, the carrier transport properties after HC stress were also examined based on the proposed method. Moreover, method has been applied to examine the carrier transport and reliabilities in advanced strain-CMOS devices. In terms of the device performance, the enhancement of the drain current is strongly related to the transport parameter, the injection velocity, V(inj) which serves as a good monitor for the strain design and current enhancement. While, considering the device reliability after the HC stress, ballistic efficiency, B(sat) is responsible for the I(D) degradation as a result of the increase in interface scatterings. Finally, a roadmap of the V(inj) from those reported results has been provided which serves as a good reference for designing high performance strain-based CMOS devices.
A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement
(2009)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I(D)-RTN (Drain Current Random Telegraph Noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL, also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
(2009)
Chung, Steve S.
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Hsieh, E. R.
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Liu, P. W.
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Chiang, W. T.
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Tsai, S. H.
A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I(D.sat) current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%-1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover. PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
Effect of supercritical fluids on field emission from carbon nanotubes
(2006)
Liu, P. T.
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Tsai, C. T.
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Kin, K. T.
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Chang, P. L.
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Chen, C. M.
This paper proposes a novel method to enhance the emission characteristics of carbon nanotubes (CNTs). It is extremely possible for CNTs to adsorb moisture and other contaminants during the fabrication processes, leading to the degraded field emission characteristics. In this work, CNT emitters are activated with commonly used heating process and supercritical carbon dioxide (SCCO2) fluids technology for removing adsorbed residue moisture. Experimental results have demonstrated that the electrical stability and field emission enhancement of CNT emitters are effectively achieved by the SCCO2 fluids treatment compared to the heating process, due to the minimization of residuary moisture in CNTs.
Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Trigate MOSFETs and the Power Dissipation of SRAM
(2013-01-01)
Hsieh, E. R.
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Lin, S. T.
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Chung, Steve S.
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Huang, R. M.
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Tsai, C. T.
A new gate current variation (sIg) has been proposed for the first time and demonstrated on the trigate devices. It was found that gate current variation can serve as an indicator of the gate sidewall surface roughness. A new theory has then been developed and verified experimentally on trigate devices with various fin heights. Results show that surface roughness increases with the increasing fin height. In addition, hot carrier and NBT stresses have also been performed for trigate CMOS devices. It was found that NBTI exhibits the worst Ig variation. Finally, this theory has been tested on the SRAM to examine the standby power dissipation. Results show that the power dissipation is dominated by the pFET NBTI effect.
Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Liu, C. H.
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Chung, Steve S.
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Huang, R. M.
A new theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.
More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable Reliability
(2008)
Chung, Steve S.
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Hsieh, E. R.
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Huang, D. C.
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Lai, C. S.
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Tsai, C. H.
In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyond
(2008)
Hsieh, E. R.
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Chung, Steve S.
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Lin, Y. H.
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Tsai, C. H.
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Liu, P. W.
In this work, for the first time, an abnormal leakage current has been observed in MOSFET with 50nm channel length and beyond. This effect shows that, in an ultra-short channel MOSFET, sub-threshold swing (SS) and I(off) are decreased for back-biased nMOSFET and pMOSFET. This effect is attributed to the BJT-induced current from the source to the drain. An experimental approach has been used to verify the existence of this BJT current component. As a consequence, this BIT current can be reduced with appropriate control of the S/D-to-substrate junction. As an application of the approach to advanced embedded-SiC MOSFET with various splits, it was found that a higher band-offset of S/D-to-substrate junction will give rise to a larger the BJT ballistic transport current. This provides us important information on reducing the leakage current for advanced CMOS with 50nm and beyond.
New Observations on the Physical Mechanism of Vth-Variation in Nanoscale CMOS Devices After Long Term Stress
(2011)
Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Huang, R. M.
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Tsai, C. T.
A new effect, called random trap fluctuation(RTF), is proposed to study the impact of hot carrier stress on the device variability. It was found that not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or FN-stress, induce the V(th) variation. After the FN stress, it was found that Vth variation is worse in pMOSFETs due to stress-induced interface traps. While, under the HC stress, different Vth variations were found for nMOSFETs and pMOSFETs. The Vth variation is enhanced in pMOSFETs due to RTF and reduced in nMOSFET as a result of the Trap Blocking Effect (TBE). RTF in pMOSFET might be the dominant factor of CMOS reliability for future generations.
New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI Reliabilities for 65nm node CMOS devices and beyond
(2006)
Chung, Steve S.
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Huang, D. C.
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Tsai, Y. J.
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Lai, C. S.
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Tsai, C. H.
In this paper, new observations on the uniaxial and biaxial strain-induced hot carrier reliability and/or NBTI in nMOSFET and pMOSFET respectively have been reported for the first time. Uniaxial and biaxial strained nMOSFET and pMOSFET have been extensively examined. Different mechanisms are responsible for different strains in nMOSFET and pMOSFET. For the nMOFETs, it was found that uniaxial strain device has comparable HC reliability with the control device, while biaxial SiGe-strained device exhibits a much worse reliability. This is related to a large impact ionization rate in a biaxial strain which leads to a much worse reliability. For the pMOSFETs, either uniaxial or biaxial strained device shows a comparable amount of HC degradation, while SiGe S/D strained structure might be better considering process complexity, performance, and reliability Although NBTI is still a great concern in SiGe S/D devices, embedded SiGe S/D technique can improve greatly the device NBTI reliability. These results provide a valuable guideline for the present 65nm and beyond CMOS device design with focus on the strain engineering.
Reliability of ALD Hf-based high K gate stacks with optimized interfacial layer and pocket implant engineering
(2007)
Mao, A. Y.
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Lin, W. M.
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Yang, Cw.
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Hsieh, Y. S.
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Cheng, L. W.
Reliability of ALD (Atomic Layer Deposition) HfSiON high K gate stacks is greatly enhanced with a property engineered IL (Interfacial Layer) between the gate dielectrics and the Si substrate. We report that the HfSiON, while deposited on an optimized plasma-based IL containing [N], exhibits strong resistance to the bombardment from heavy pocket implant species, achieving significantly reduced leakage and excellent reliability characteristics, compared to the HfSiON without an optimized IL and to the silicon oxynitride control wafers.
Technology roadmaps on the ballistic transport in strain engineered nanoscale CMOS devices
(2007)
Chung, Steve S.
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Tsai, Y. J.
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Tsai, C. H.
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Liu, P. W.
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Lin, Y. H.
As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the ION current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100nm regime.
The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology
(2008)
Hsieh, E. R.
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Chang, Derrick W.
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Chung, S. S.
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Lin, Y. H.
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Tsai, C. H.
In this paper, the device performance in terms of its transport charactertitics and reliability of the MOS devices on the SOI and strained-SOI have been examined. For the first time, both the transport and reliability characteristics have been established from. experimental SOI and SSOI nMOSFETs. It was characterized by two parameters, the ballistic efficiency and the injection velocity. Experimental verifications on rMOSFETs with both technologies with tensile-stress enhancement have been made. For SSOI devices, it shows the expected drain current enhancements. For the reliability evaluations, SOI shows a smaller lattice such that it exhibits a much worse hot carrier (HC) reliability, while SSOI device shows a poorer interface quality verified from the FN-stress experiment. In general, although SSOI exhibits a worse interface quality while its reliability is much better than that of SOI's. Moreover, SSOI device shows a very high injection velocity as a result of the high strain of the device which makes it successful for drain current enhancement.
The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientations
(2007)
Tsai, Y. J.
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Chung, Steve S.
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Liu, P. W.
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Tsai, C. H.
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Lin, Y. H.
The channel backscattering and injection velocity of carriers in advanced CMOS devices are the two key parameters for achieving high drain current enhancement. For the first time, an extensive study of these transport parameters for different substrate orientations has been evaluated for both nMOSFET and pMOSFET. By suitably choosing the substrate orientation, it may achieve a reduced backscattering and an increased injection velocity, which is preferable for designing high performance logic CMOS devices. Results show that, in pMOSFET, (110) substrate is preferred and current enhancement can be greatly enhanced in the < 112 > channel. In comparison, (110) substrate in nMOSFET has an adverse effect in reducing driving current as a result of poorer transport characteristics. Therefore, (100) substrate is expected for nMOSFET design. A guideline is then summarized for the optimum design of high performance CMOS devices.
The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
(2015)
Hsieh, E. R.
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Huang, Z. H.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
For the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<50 mu A), fast speed (similar to 20 mu sec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era.
The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
(2014)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
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Liu, C. H.
For the first time, the breakdown path induced by BTI stress can be traced from the RTN measurement. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path. It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown paths are revealed. The soft-breakdown path is in a shape like spindle, while the hard breakdown is like a snake-walking path. These two breakdown paths are reflected in a two slopes TDDB lifetime plot. These new findings on the breakdown-path formation will be helpful to the understanding of the reliability in HK CMOS devices.
The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
(2014-01-01)
Wu, P. C.
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Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
A comprehensive analysis on the BTI induced RTN traps in high-k(HK) CMOS devices have been investigated in inversion (inv.) and accumulation (acc.) modes. The combination of two modes for RTN measurement provides a wide range of energy window in high-k gate dielectric, in which a simple extraction method of RTN analysis has been adopted to analyze the gate dielectric dual-layer of advanced HK devices. The results show that inversion mode measurement can only identify the RTN traps in the channel region, which is related to the V-th degradation. While, accumulation mode may detect the traps inside the gate-drain overlap region which provides better understanding of GIDL current. This basic understanding is of critical important to the quality development of HK gate dielectrics in advanced CMOS technologies.
The Observation of Trapping and Detrapping Effects in High-k Gate Dielectric MOSFETs by a New Gate Current Random Telegraph Noise (I(G)-RTN) Approach
(2008)
Chang, C. M.
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Chung, Steve S.
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Hsieh, Y. S.
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Cheng, L. W.
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Tsai, C. T.
A new method, called gate current Random Telegraph Noise (I(G) RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, I(G) RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the soft-breakdown (SBD) behavior of a device can be clearly identified. Its I(G) RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
(2015)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
In this paper, the evolution of BTI induced leakage paths has been evaluated by I-g-RTN technique and demonstrated on HK/MG CMOS devices. First, RTN measurement has been elaborated to identify the location of traps and their correlation to the leakage current. Then, the measured gate current transient can he used to analyze the formation of breakdown path. The results show that the evolution of leakage paths can be divided into three stages, i.e., (I) the early stage- only gate leakage and discrete RTN traps are observed, (2) the middle stage- the traps interacting with the percolation paths and exhibits a multi-level current variation, and (3) the last stage- the formation of breakdown path. These findings provide useful information on the understanding of gate dielectric breakdown in high-k CMOS devices.