Browsing by Author "Tsai, CS"

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Design and synthesis of activity probes for glycosidases
(2002-10-17)
Tsai, CS
;
Li, YK
;
Lo, LC
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應用化學系
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Department of Applied Chemistry
[GRAPHICS] A new synthetic route was developed for the preparation of activity probe 1 for beta-glucosidase in this study. The key glycosidation step begins with benzyl p-hydroxyphenylacetate. Benzylic functionalization for the construction of the trapping device was achieved at later stages. Probe 1 was shown to be able to label the target enzyme. This cassette-like design offers great flexibility for future alterations. It would allow the synthetic scheme to expand to other glycosidase probes with different linker/reporter combinations.
Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit
(2003)
Ker, MD
;
Tsai, CS
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電機學院
;
College of Electrical and Computer Engineering
This paper presents a 2.5V/5V mixed-voltage CMOS I/O buffer that does not need a CMOS technology with a dual-oxide option and complex bias circuits. The proposed mixed-voltage I/O buffer with simpler circuit structure can overcome the problems of leakage current and gate-oxide reliability, which occurring in the conventional CMOS I/O buffer. In this work, the new proposed design has been realized in a 0.25-mum CMOS process, but it can be easily scaled toward 0.18-mum or 0.15-mum processes to serve a 1.8V/3.3V mixed-voltage I/O interface.
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
(2006-05-01)
Ker, MD
;
Chen, SL
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Tsai, CS
;
電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new charge pump circuit with consideration of gateoxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-mu m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications
(2005)
Ker, MD
;
Chen, SL
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Tsai, CS
;
電機學院
;
College of Electrical and Computer Engineering
A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltage-tolerant applications is proposed. The new proposed I/O buffer can receive the input signals with the voltage swing twice as high as the normal power supply voltage (VDD), which has been fabricated in a 0.25-mu m CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-mu m (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.
Impact of a large earthquake on a GPS network: The case of the 1999 Chi-Chi, Taiwan earthquake
(2002-04-01)
Kuo, LC
;
Yu, SB
;
Hsu, VJ
;
Hou, CS
;
Lee, YH
On 20 September 1999, Taiwan was hit by the largest inland earthquake (M-w = 7.6) in the last century resulting in an 80-kilometre thrust rupture almost directly along the existing Chelungpu fault. Here, we estimated the coordinates of the GPS stations by using the annual epoch-observed and permanent continuously-recorded GPS data covering the 1992-1999 period Taking into account the effects of secular motion and post-deformation, we calculated the corrected coseismic displacements. Relatively large coseismic displacements of 8-9 in in the horizontal and vertical components were found in the northern part of the fault. Stations on the hanging wall shifted horizonatly 2-9 in in the NW direction and decreased in magnitude from west to east. On the other hand, displacements on the footwall were less than 2 in in the SE direction hid increased from west to east. The size of the zone overlapping the hanging wall and the foowall showed a decrease of 796 ppm in 494 km(2). This is in direct contrast to areas near the fault which increased in size from 13 to 23 7 ppm. Significant postseismic deformations were also observed in data from the existing 44 permanent stations and 7 temporary stations. Additionally, large postseismic deformations of 10-20 cm were found at stations SUAM, 100 7 and YUSN within 10 months.
Plasma charging damage during contact hole etch in high-density plasma etcher
(2000-12-01)
Tsui, BY
;
Lin, SS
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Tsai, CS
;
Hsia, CC
;
電子工程學系及電子研究所
Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler-Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully. (C) 2000 Elsevier Science Ltd. All rights reserved.
Stateful session handoff for mobile WWW
(2006-05-08)
Hsieh, MD
;
Wang, TP
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Tsai, CS
;
Tseng, CC
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資訊工程學系
This paper proposes a web session handoff system that can hand over not only stateless but also stateful sessions between homogenous and heterogeneous user devices to enable uninterrupted and seamless web access. The proposed system adopts a proxy-based approach and an optional client-assisted scheme in order to track and hand over session information. In the proposed system, a session is registered at a User Agent Proxy (UAP) and then tracked by the UAP so that the session can be handed over from one device via the UAP to another device. In addition to session information tracked by a UAP, the UAP can hand over more comprehensive session information by using the client-assisted scheme. Compared with client-based approaches, our design has several advantages, such as less modification to user devices, practicability, and fault tolerance. We have implemented a UAP on a PC and client programs for both PC and PDA. The implementation can successfully hand over between PC and PDA a stateful session for online shopping applications. (C) 2005 Elsevier Inc. All rights reserved.