Browsing by Author "Tsai, CW"

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A comparative study of SILC transient characteristics and mechanisms in FN stressed and hot hole stressed tunnel oxides
(1999)
Zous, NK
;
Wang, TH
;
Yeh, CC
;
Tsai, CW
;
Huang, CM
The mechanisms and transient characteristics of hot hole stress and FN stress induced excess leakage currents in tunnel oxides are investigated. Hot hole SILC is found to have a more pronounced transient effect. The transient is attributed to positive oxide charge detrapping and thus annihilation of positive charge-assisted tunneling current. The positive charge assisted tunneling current can be annealed by substrate hot electron injection. The DC and transient components in FN SILC are also discussed.
A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs - From single electron emission to PBTI recovery transient
(2006-05-01)
Wang, TH
;
Chan, CT
;
Tang, CJ
;
Tsai, CW
;
Wang, HCH
A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.
Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias
(2000)
Chiang, LP
;
Tsai, CW
;
Wang, T
;
Liu, UC
;
Wang, MC
Enhanced hot carrier degradation is observed in DTMOS-like operation mode. This phenomenon is attributed to Auger recombination assisted hot electron process. Measured hot electron gate current and light emission spectrum in nMOSFETs provide evidence that the high-energy tail of channel electrons is increased by the application of a positive substrate bias. As opposed to conventional hot carrier degradation, the Auger enhanced degradation exhibits positive temperature dependence and is more significant at low drain bias.
Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias
(2003-04-01)
Tsai, CW
;
Chen, MC
;
Ku, SH
;
Wang, TH
;
電子工程學系及電子研究所
Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forward-biased substrate and provide for Auger recombination with electrons in the channel thus substantially increasing channel hot electron energy. Measured hot electron gate-current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten time's more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.
Mechanism for slow switching effect in advanced low-voltage, high-speed Pb(Zr1-XTiX)O-3 ferroelectric memory
(2005-06-01)
Tsai, CW
;
Lai, SC
;
Yen, CT
;
Lien, HM
;
Lung, HL
Slow-switching effect in PZT ferroelectric memory under low-voltage and high-speed operation is observed. The slow-switching effect becomes worse at lower operation voltage and elevated temperature. This effect significantly reduces the sensing margin and causes severe reliability issue for advanced ferroelectric memory, particularly for low-voltage and high-speed applications. This slow-switching effect is believed to be attributed to slowing down of polarization switching caused by band bending from Schottky built-in potential at the electrode/ferroelectric interface. The proposed mechanism is supported by the polarity dependence in an asymmetric LNO/PZT/Pt sample.
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs
(2003)
Wang, TH
;
Tsai, CW
;
Chen, MC
;
Chan, CT
;
Chiang, HK
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4nm) pMOS is observed. This result is believed due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.
Single-electron emission of traps in HfSiON as high-k gate dielectric for MOSFETs
(2005)
Chan, CT
;
Tang, CJ
;
Kuo, CH
;
Ma, HC
;
Tsai, CW
A novel method for characterizing MOSFETs with HfSiON high-k gate dielectric is demonstrated for the first time by direct measurement of single-electron de-trapping. Individual high-k trapped electron emission is recorded, which is manifested by the step-like evolution of channel current. The physical path of electron de-trapping can be identified from the emission time of such single-electron de-trapping. The dependence of charge emission time on gate voltage and temperature is measured. An analytical model based on thermally assisted tunneling can predict the emission time behavior, trap activation energy, trap density, and total available traps in high-k gate dielectric.
Soft breakdown enhanced hysteresis effects in ultra-thin oxide SOI nMOSFETs
(2002)
Chen, MC
;
Tsai, CW
;
Gu, SH
;
Wang, TH
;
電子工程學系及電子研究所
The impact of soft breakdown location on V, hysteresis in partially depleted SOI nMOSFETs with ultra-thin oxide (1.6nm) is investigated. Two breakdown enhanced hysteresis modes are identified. In a channel breakdown MOSFET, excess holes attributed to valence electron tunneling flow to the floating body and thus cause V, hysteresis in gate bias switching. As a contrast, in a drainedge breakdown device, enhanced V, hysteresis is observed during drain bias switching because of increased band-to-band tunneling current.
Substrate bias dependence of breakdown progression in ultrathin oxide pMOSFETs
(2003-04-01)
Tsai, CW
;
Chen, MC
;
Gu, SH
;
Wang, T
;
電子工程學系及電子研究所
Negative substrate bias-enhanced oxide breakdown (BD) progression in ultrathin oxide (1.4 nm) pMOS is observed. The enhanced progression is attributed to the increase of hole-stress current resulting from BD-induced, channel-carrier heating. The carrier temperature extracted from the spectral distribution of hot-carrier luminescence is around 1300 K. The substrate bias dependence of post-BD hole-tunneling current is confirmed from measurement and calculation. The observed phenomenon is particularly significant to ultrathin gate oxide reliability in floating substrate (SOI) and forward-biased substrate devices.
Transient effects of positive oxide charge on stress-induced leakage current in tunnel oxides
(1999-08-02)
Zous, NK
;
Wang, TH
;
Yeh, CC
;
Tsai, CW
;
Huang, CM
The role of positive oxide charge in excess low-level leakage current in tunnel oxides induced by Fowler/Nordheim stress is investigated. A correlation between stress-induced gate current and substrate current in an n-channel metal-oxide-semiconductor field-effect transistor is observed. Both the gate current and the substrate current exhibit a significant transient effect. The mechanisms of the stress-induced currents and their field dependence are explored. Positive oxide charge tunnel detrapping is found to be the cause of the observed transient behavior in the two currents. The stress-created positive oxide charge can be significantly annealed by substrate hot electron injection. (C) 1999 American Institute of Physics. [S0003-6951(99)02226-3].
Valence-band tunneling enhanced hot carrier degradation in ultra-thin oxide nMOSFETs
(2000)
Tsai, CW
;
Gu, SH
;
Chiang, LP
;
Wang, TH
;
Liu, YC
Enhanced hot carrier degradation with stress V-g in the valence-band tunneling regime is observed. This degradation is attributed to channel hole creation by valence-band electron tunneling. The created holes provide for Auger recombination with electrons in the channel and thus increase hot electron energy. The valence-band tunneling enhanced hot carrier degradation becomes more serious as gate oxide thickness is reduced. In ultra-thin gate oxide nMOSFETs, our result shows that the valence-band tunneling enhanced degradation, as opposed to max. Tb stress induced degradation, exhibits positive dependence on substrate bias. This phenomenon may cause a severe reliability issue in positively biased substrate or floating substrate devices.