Browsing by Author "Tsai, Chang-Hung"

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A 2 GOPS Quad-Mean Shift Processor with Early Termination for Machine Learning Applications
(2014-01-01)
Tsai, Chang-Hung
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Lee, Hui-Hsuan
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Yu, Wan-Ju
;
Lee, Chen-Yi
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電機工程學系
This paper proposes a 2 GOPS quad-mean shift processor (Q-MSP) architecture for data clustering and machine learning applications. By exploiting the linear approximation approach and early termination mechanism, the proposed algorithm can reduce 70% and 40% computational complexity, respectively. Moreover, 4 mean shift processor cores are integrated into the proposed architecture to support parallel processing to further improve system performance. Implemented in Xilinx Virtex-7 FPGA, this architecture occupies 65k LUTs and 3.3MB block memory to achieve 2 GOPS throughput operated at 125MHz.
A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications
(2017-10-01)
Tsai, Chang-Hung
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Yu, Wan-Ju
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Wong, Wing Hung
;
Lee, Chen-Yi
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電子工程學系及電子研究所
An energy-efficient restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning and Internet of Things (IoT) applications in this paper. To train a neural network (NN) model, the RBM structure is applied to supervised and unsupervised learning, and a multi-layer NN can be constructed and initialized by stacking multiple RBMs. Featuring NN model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators for power reduction, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism for learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology, the proposed RBM-P chip costs 2.2 M gates and 128 kB SRAM with 8.8 mm(2) area. Operated at 1.2 V and 210 MHz, this chip achieves 7.53G neuron weights (NWs) and 11.63G NWs per second with 41.3 and 26.7 pJ per NW for learning and inference, respectively.
A 41.3pJ/26.7pJ Per Neuron Weight RBM Processor for on-Chip Learning/Inference Applications
(2016-01-01)
Tsai, Chang-Hung
;
YU, Wan-Jun
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Wong, Wing Hung
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
A restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning applications in this paper. Featuring neural network (NN) model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism in learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology', the proposed RBM-P chip costs 2.2M gates and 128kB SRAM with 8.8mm(2) area. Operated at 1.2V and 210MHz, this chip respectively achieves 114.3x and 3.9x faster processing time than CPU and GPGPU. And the proposed RBM-P chip consumes 41.3pJ and 26.7pJ per neuron weight (NW) for learning and inference, respectively.
A 446.6K-Gates 0.55-1.2V H.265/HEVC Decoder for Next Generation Video Applications
(2013)
Tsai, Chang-Hung
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Wang, Hsiuan-Ting
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Liu, Chia-Lin
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Li, Yao
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Lee, Chen-Yi
An architecture of H. 265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H. 265/HEVC video decoder occupies an area of 1.60x1.98mm(2) to achieve 1080p@30fps and 720p@30fps real-time decoding with power consumption of 36.90 and 9.57mW.
A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System
(2015-11-01)
Tsai, Chang-Hung
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Chih, Yu-Ting
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Wong, Wing Hung
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
A hardware-efficient sigmoid function calculator with adjustable precision for neural network and deep-learning applications is proposed in this brief. By adopting the bit-plane format of the input and output values, the computational latency of the processing time can be dynamically reduced according to the user configuration. To reduce the hardware cost, the coefficients used to calculate the sigmoid value can be shared for multiple calculators without any structural hazard. In addition, the restricted constraint is applied in the coefficients\' training stage to further simplify the computation in the calculation stage with a negligible quality loss. A test module is designed for the proposal and operated at 300 MHz to achieve 75 million sigmoid calculations per second. Implemented in 90-nm CMOS technology, the core of the calculator costs 1663 gates, and a 1-kb globally shared memory is used to store the coefficients.
A Memory-Efficient Architecture for Intra Predictor and De-Blocking Filter in Video Coding System
(2012)
Liu, Chia-Lin
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Tsai, Chang-Hung
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Wang, Hsiuan-Ting
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Li, Yao
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Lee, Chen-Yi
In the hardware architecture of the H. 264/AVC video coding systems, the storage size of the intra predictor and deblocking filter occupies a great portion of the internal memory size in the video coding. However, the higher resolution video costs huge internal memory size to store pixels to predict block data and eliminate the blocking effect, especially for the next-generation video applications which target resolution is Ultra-HD (8Kx4K). In this article, a memory-efficient architecture for intra predictor and de-blocking filter has been proposed which can roughly reduce up to 19% internal memory usage to efficiently reduce the decoder size and power consumption, and the sequential-interleaving memory architecture has also been adopted in the proposed architecture to solve the memory access conflict during video decoding. A test module is designed for the proposal and operates at 200 MHz for real-time processing with 85.1 K gates and 8.4 KB SRAM in 90nm CMOS technology.