Browsing by Author "Tsai, Chia-Chun"

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Design of a digit-serial multiplier over GF(2(m)) using a karatsuba algorithm
(2019-10-03)
Lee, Trong-Yen
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Liu, Min-Jea
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Huang, Chia-Han
;
Fan, Chia-Chen
;
Tsai, Chia-Chun
A Karatsuba algorithm (KA) is used for highly accurate multiplication using a divide and conquer approach. A new approach to a polynomial digit-serial multiplier that uses an optimal digit size (d) for KA decomposition has recently been proposed. In this study, the proposed architecture uses three small multipliers to derive an optimal digit size (d) for the case of trinomial based fields. Using the proposed KA decomposition, this study establishes five types of sub-quadratic multipliers, which are, the recombined m-bit exponentiation multipliers using a KA. The theoretical results show that the proposed polynomial exponentiation multipliers that use a KA have a value of (d x m)/2 and involve significantly less time and area complexity than existing digit-serial multipliers. The simulation results for the proposed method demonstrate a respective 68.20%, 77.37%, 72%, 83.18%, 36.66% decrease in area x time over GF(2(36)), GF(2(84)), GF(2(126)), GF(2(204)) and GF(2(340)).
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform
(2016-03)
Lai, Shin-Chi
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Juang, Wen-Ho
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Lee, Yueh-Shu
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Chen, Shin-Hao
;
Chen, Ke-Horng
This brief presents a hybrid structure to effectively compute the variable-length Fourier transform by employing the recursive and radix-2(2) fast algorithm. After applying a hardware-sharing scheme to both fast algorithms, the proposed method not only improves the drawback of higher hardware cost in implementation but also retains the regular and flexible nature of recursive discrete Fourier transform (RDFT). The proposed hardware accelerator only costs four real multipliers and ten real adders with a greater reduction (86.7% and 66.7%, respectively) than Kim et al.\'s design. In addition, the number of multiplications and additions for 256-point DFT computations can be reduced by 38.6% and 70%, respectively, compared to Lai et al.\'s recent approach. For accuracy analysis, the SNR value of the proposed design, at least, is 4 dB higher than the other RDFT designs. Considering a whole evaluation, a very-large-scale integration chip design was further fabricated using TSMC 0.18-mu m 1P6M CMOS process. The core size was only 660 x 660 mu m(2), and the measured power consumption was 8.8 mW @ 25 MHz. The result shows that the proposed chip included data memory is 1.38 times the computational efficiency per unit area of Lai et al.\'s work. Therefore, it will be the state-of-the-art RDFT processor in the application of various variable-transform-length digital signal processing issues.