Browsing by Author "Tsai, Chia-Ming"

Now showing 1 - 18 of 18

A 0.6V, 1.3GHZ DYNAMIC COMPARATOR WITH CROSS-COUPLED LATCHES
(2015)
Kuo, Bo-Jyun
;
Chen, Bo-Wei
;
Tsai, Chia-Ming
;
交大名義發表
;
National Chiao Tung University
This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=10(-9), the comparator achieves 143fJ at 3.3GHz and a 0.9V supply, which decreases to only 49fJ at 1.3GHz and a 0.6V supply. Both measured results are based on the input differential voltage of only 4.2mV. The comparator is implemented in 65nm CMOS technology and the chip area of the core circuit occupies 265 mu m(2).
A 10 Gb/s Adaptive Cable Equalizer Using Phase Detection Technique in 0.13 mu m CMOS Technology
(2012)
Chen, Kuang-Ren
;
Tsai, Chia-Ming
;
You, Sheng-Kai
;
Li, An-Siou
;
Chen, Wen-Tsao
This paper presents an adaptive cable equalizer employing a time-domain approach called the phase detection technique in 0.13 mu m CMOS technology. The equalizer can compensate a 24-inch microstrip on an FR4 PCB, which has an 18dB channel loss at 5GHz. Meanwhile it also avoids offset-sensitive rectifiers which normally exist in conventional equalizers. The proposed adaptive cable equalizer consumes 39mW excluding the output buffer from a 1.5-V supply voltage and the measured BER is less than 10(-13).
A 10Gb/s 44.2 dB Adaptive Equalizer with Duobinary Tracking Loop in 0.18 mu m CMOS
(2014-01-01)
Chang, Po-Hsuan
;
Li, An-Siou
;
Tsai, Chia-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an adaptive equalizer that converts the attenuated signal into Duobinary signaling scheme, combined with automatic Duobinary tracking technique to produce high quality Duobinary signal for simplifying the Duobinary decoding process and achieving higher data rate. The adaptive equalizer uses dual gain-mode topology that allows higher gain when the received signal is highly attenuated, and allows lower power consumption when the received signals pass through low-attenuation channel. A background offset cancellation loop circuit is added to increase the clock phase margin of the equalizer. The chip is fabricated in 0.18 mu m CMOS technology and operates at data rate of 10 Gb/s. The measurement results show that the equalizer recovers data properly for FR-4 trace with length ranging from 3 inches to 66 inches. The equalizer achieves clock phase margin of 58 % for 66-inch channel with BER less than 10(-12) and consumes power of 28.4 mW under high gain mode with 1.8V power supply.
A 13.5Gb/s 20.5dB Adaptive Equalizer With Simplified Overshoot Control in 65nm CMOS
(2014)
You, Sheng-Kai
;
Wei, Wey-Tin
;
Tsai, Chia-Ming
;
Sang, Tzu-Hsien
;
電子工程學系及電子研究所
This paper presents a simplified overshoot control technique suitable for equalization of NRZ data pattern. Compared to conventional design, the generation of overshoot reference voltage is greatly simplified by using a top holder with swing-dependent built-in offset. Fabricated in a 65nm CMOS technology, the adaptive equalizer is capable of running at 13.5Gb/s over a 20-inch FR4 trace with a loss of 20.5dB at 6.75GHz while consuming 17mW from a 1.2V supply.
A 3-GHz, 22-ps/dec Dynamic Comparator using Negative Resistance Combined with Input Pair
(2010-01-01)
Chen, Bo-Wei
;
Wang, Jen-Peng
;
Tsai, Chia-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high speed, low delay/log(Delta Vin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(Delta Vin) of the comparator is 22ps/dec and consumes 213 mu W at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.
A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 mu m CMOS Technology
(2009-10-01)
Tsai, Chia-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
By combining an appropriate differential-sensing scheme with the bootstrapping technique, this paper presents a self-compensated design topology which is shown to be effective at reducing the loading effects due to the photodiode and the ESD protection circuit at the differential inputs. The built-in offset creation technique is introduced to overcome voltage headroom limitation. Furthermore, the negative impedance compensation is employed to enhance the gain-bandwidth product. The IC is shown to be tolerant of ESD protection circuit with 0.5 pF equivalent capacitance at the differential inputs. While connected to an InGaAs PIN photodiode exhibiting 0.8 pF equivalent capacitance, the implemented IC has achieved a differential transimpedance gain of 3.5 k Omega and a -3 dB bandwidth of 1.72 GHz. At a data rate of 3 Gb/s, the measured dynamic range is from -20 dBm to +0 dBm at a bit-error rate of 10(12) with a 2(31) - 1 pseudorandom test pattern. The negative impedance compensation is shown to achieve enhancement factors of 4.5 dB and 520%, respectively, for transimpedance gain and -3 dB bandwidth. The IC totally consumes 40 mW from a 1.8 V supply.
A 6Gb/s 40dB Burst-Mode Digitally Adaptive Equalizer with Reference-Calibrated Overshoot Control
(2013-01-01)
You, Sheng-Kai
;
Chang, Po-Hsuan
;
Tsai, Chia-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a burst-mode equalizer for the communication incorporating electrical idle state which is usually used for power management. Fabricated in 0.18 mu m CMOS technology, the proposed equalizer can compensate over 90-inch microstrip on an FR4 PCB, which has a 40dB loss at 3GHz. The proposed overshoot control scheme with reference calibration can reduce offset-induced error on detections and is observed to achieve jitter improvement of 0.06UI. With the help of envelope detector and digital adaptation, the reaction time under burst-mode transmission is 5.5ns or 33bit-time. The equalizer consumes 26.7mW from a 1.8V supply and measured BER is less than 10(-12).
A 6Gb/s Adaptive Equalizer Using Overshoot Control in 0.18 mu m CMOS Technology
(2012)
Nee, Hsu-Che
;
Tsai, Chia-Ming
;
You, Sheng-Kai
;
Chen, Wen-Tsao
;
電子工程學系及電子研究所
This work proposes an adaptive equalizer employing a new overshoot control for achieving optimized equalization. The proposed overshoot detection scheme obviates the need for slicers to achieve high-speed operation with low power dissipation. The circuit adapts to FR4 trace lengths for up to 40 inches. The measurement results show that the equalizer achieves a good eye performance while consuming 40mW from a 1.8V supply.
A 93dB-ohm 2.5Gb/s CMOS burst-mode optical receiver with internal reset creation
(2008)
Lin, Yi-Shing
;
Tsai, Chia-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a 2.5Gb/s burst-mode optical receiver with quick response in a 0.18 mu m CMOS process. A dual-mode transimpedance amplifier is used to achieve a dynamic range of 19dB. The internal reset signal created by the limiting amplifier is more reliable due to the increased net gain compared to prior designs. The receiver achieves 93dB Omega total differential transimpedance gain, 1.56GHz optical bandwidth, and fast response time of less than 10ns. This IC dissipates 146mW from a 1.8V supply.
A COMPARATIVE STUDY ON ATTENTION-BASED RATE ADAPTATION FOR SCALABLE VIDEO CODING
(2009)
Tsai, Chia-Ming
;
Lin, Chia-Wen
;
Lin, Weisi
;
Peng, Wen-Hsiao
;
資訊工程學系
We conduct subjective tests to evaluate the performance of scalable video coding with different spatial-domain bit-allocation methods, visual attention models, and motion feature extractors in the literature. For spatial-domain bit allocation, we use the selective enhancement and quality layer assignment methods. For characterizing visual attention, we use the motion attention model and perceptual quality significant map. For motion features, we adopt motion vectors from hierarchical B-picture coding and optical flow. Experimental results show that a more accurate visual attention model leads to better perceptual quality. In cooperation with a visual attention model, the selective enhancement method, compared to the quality layer assignment, achieves better subjective quality when an ROI has enough bit allocation and its texture is not complex. The quality layer assignment method is suitable for region-wise quality enhancement due to its frame-based allocation nature.
Anti-interference single-photon LiDAR using stochastic pulse position modulation
(2020-01-15)
Tsai, Chia-Ming
;
Liu, Yung-Chien
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This Letter introduces an anti-interference single-photon light detection and ranging (LiDAR) system with photon-driven stochastic pulse position modulation. A photon arrival sequence with a programmable minimum interval time and trigger rate was proposed to trigger laser pulses, thus providing true nature-based randomness in modulation which is beneficial for achieving bet ter anti-interference capability. In the proposed LiDAR system, two complementary metal-oxide-semiconductor single-photon avalanche diodes (SPADs) are used as an optical receiver and to generate a random trigger pattern of a pulsed laser. To prevent the range ambiguity problem, an interval-time filter capable of controlling the minimum interval time is integrated into the LiDAR system. A trigger rate controller capable of adaptively controlling the driving voltage of a light-emitting diode coupled with the SPAD responsible for the generation of the random trigger sequence is also integrated for achieving a precise control of trigger rate. Finally, a proof-ofconcept demonstration was provided through experiments, and the obtained results were consistent with theoretical predictions. At an effective trigger rate of 800 kHz,, an excellent suppression ratio of 56.2 dB has been achieved in the presence of a 1 MHz periodic interference. (C) 2020 Optical Society of America
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
;
Liu, Jen-Chieh
;
Shen, Yu-Lin
;
Chou, Teyuh
;
Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Constant Excess Bias Control for Single-Photon Avalanche Diode Using Real-Time Breakdown Monitoring
(2015-08-01)
Chang, Po-Hsuan
;
Tsai, Chia-Ming
;
Wu, Jau-Yang
;
Lin, Sheng-Di
;
Kuo, Ming-Ching
A monolithic constant excess bias control circuit for single-photon avalanche diode (SPAD) in standard 0.18-mu m CMOS technology is reported. The proposed real-time breakdown monitoring technique is incorporated into a passive-quenching-active-reset circuit. A sample-and-hold circuit samples the breakdown level of SPAD through well-defined sampling phase. Following the sample-and-hold circuit, the level shifter with voltage shifting defined by predetermined excess bias provides the reset voltage of SPAD. The design operates the SPAD under constant excess bias and effectively mitigates the impact of the process-voltage-temperature variation by maintaining the optimal excess bias condition.
Crosstalk Between Single-Photon Avalanche Diodes in a 0.18-mu m High-Voltage CMOS Process
(2018-02-01)
Wu, Dai-Rong
;
Tsai, Chia-Ming
;
Huang, Yi-Hsiang
;
Lin, Sheng-Di
;
電子工程學系及電子研究所
Crosstalk between single-photon avalanche diodes (SPADs) fabricated by the standard CMOS process is extensively investigated. The dependence of device structure, device-to-device distance, and bias voltage on crosstalk has been experimentally studied. Our work reveals that direct-path optical crosstalk dominates in these CMOS SPADs, which is also confirmed with the first time-correlated crosstalk measurement. This work is valuable for SPAD array design and optimization in CMOS technology.
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
(2018-03-01)
Chang, Chih-Cheng
;
Chen, Pin-Chun
;
Chou, Teyuh
;
Wang, I-Ting
;
Hudec, Boris
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.
Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes
(2020-01-01)
Hsieh, Chin-An
;
Tsai, Chia-Ming
;
Tsui, Bing-Yue
;
Hsiao, Bo-Jen
;
Lin, Sheng-Di
Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication.
Time-Correlated Crosstalk Measurements between CMOS Single-Photon Avalanche Diodes
(2018-01-01)
Wu, Dai-Rong
;
Tsai, Chia-Ming
;
Lin, Sheng-Di
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We investigate time-resolved crosstalk probability between single-photon avalanche diodes in CMOS technology. The time-correlated crosstalk measurements reveal an unusual double-peak feature. This behavior becomes more significant at higher excess bias voltages and shorter device-to-device distance and its physical reason will be discussed.
Time-of-Flight Estimation for Single-Photon LIDARs
(2016-01-01)
Sang, Tzu-Hsien
;
Tsai, Chia-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Light detection and ranging (LIDAR) technologies have been in spot light for some time due to its tremendous potential of enabling applications such as advanced driver assistance systems (ADAS), virtual reality (VR), and localization in wireless networks, etc. Single-photon avalanche diode (SPAD) is a very attractive choice as light detectors in LIDAR due to its high sensitivity. Meanwhile successful signal detection in SPAD needs to overcome issues such as noise due to background illuminance and detection reliability. In this paper, a SPAD-based LIDAR system is planned, a probabilistic model of light detection with SPAD is built, and a near Maximum Likelihood (ML) algorithm is developed to estimate the time-of-flight. Simulations using measured light-pulse power profiles demonstrate that the near ML approach outperforms popular range-finding algorithms. The probabilistic formulation also opens the door of developing machine-learning algorithms for LIDARs to operate in drastically varying environments.