Browsing by Author "Tsai, Chun-Jen"

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A double-issue java processor design for embedded applications
(2007)
Ko, Hou-Jen
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
Java applications for embedded systems are becoming popular today. CLDC/MIDP is the standard application platform for mobile phones while CDC/PBP is the emerging application platform for next generation digital TV set-top boxes. Although software-based Java Virtual Machines (VM) are prevalent, most of these VMs require a host processor running at much higher clock rate than 300MHz to reach reasonable performance. This is beyond the recommended specification of handsets and set-top boxes. In this paper, we have proposed a double-issue java processor for embedded systems. The design is not tied to any host processors and can be used as an efficient binary execution engine for a full Java Runtime Environment implementation. When synthesized on a Virtex IV FPGA (4VFX12FF66-10), the RTL model can reach over 100MHz and consumes less than 22% resources of the device.
A Hardwired Priority-Queue Scheduler for a Four-Core Java SoC
(2018-01-01)
Tsai, Chun-Jen
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Lin, Yan-Hung
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資訊工程學系
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Department of Computer Science
This paper presents the design and implementation of a hardwired thread scheduler circuit with multi-level priority queues for a four-core Java application processor. A hardwired thread scheduler is much more efficient than the software thread scheduler in a software OS kernel, such as Linux. Since the hardware scheduler can operate in parallel with the processor cores, complex scheduling decisions can be made while the processor cores are running applications. In addition, single-cycle context-switching is possible and no processor core has to waste time running the scheduler. Full-system implementation of a four-core Java processor with the hardware scheduler has been verified using a Xiliox Kintex-7 FPGA device. Performance evaluations show that the proposed system scales up very well and is promising for deeply-embedded multi-thread applications such as the automatic driver assistance systems or the drones.
A Java Processor IP Design for Embedded SoC
(2015-03-01)
Tsai, Chun-Jen
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Kuo, Han-Wen
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Lin, Zigang
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Guo, Zi-Jing
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Wang, Jun-Fu
In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.
A Storage Device Emulator for System Performance Evaluation
(2015-12-01)
Wu, Ming-Ju
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
The performance and characteristics of the storage devices used in embedded systems can have a great influence on the overall end user experience. When building embedded systems or designing new storage device components, it is important for the designers to be able to evaluate how storage devices of different characteristics will affect the overall system performance. Storage device emulation enables a system\'s performance to be evaluated with simulated storage devices that are not yet available. In storage device emulation, the emulated storage device appears to the operating system (OS) as a real storage device and its service timings are determined by a disk model, which simulates the behavior of the target storage device. In the conventional storage device emulators, because the OS is running continuously in the real-time domain, the amount of time that the emulators can spend on processing each I/O request is limited by the service time of each corresponding I/O request. This timing constraint can make emulating high-speed storage devices a challenge for the conventional storage device emulators. In this article, we propose an OS state pausing approach to storage device emulation that can overcome the timing constraints faced by the conventional storage device emulators. By pausing the state of the OS while the storage device emulator is busy, the proposed emulator can spend as much time as it needs for processing each I/O request without affecting the performance of the emulated storage device as perceived by the OS. This allows the proposed storage device emulator to emulate storage devices that would otherwise be challenging or even impossible for the conventional storage device emulators. In addition, the main task of storage device emulation is offloaded to an external computer to minimize the impact of the emulation workload on the target machine. The proposed storage device emulator is implemented with the Linux OS1 on an embedded system development board. Experimental results show that the full-system performance benchmarks measured with the proposed storage device emulator are within 2% differences compared to the results of the reference system.
An Efficient Application Processor Architecture for Multicore Software Video Decoding
(2015-02-01)
Tsai, Chun-Jen
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Chen, Yan-Ting
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Tseng, Chien-Chih
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資訊工程學系
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Department of Computer Science
In this paper, we propose a new multicore application processor architecture that facilitates the adoption of the fine-granularity software-pipeline parallelism without causing an extra burden on the system bus. The proposed system-on-a-chip architecture can simultaneously support the traditional symmetric multiprocessor (SMP) and the proposed software-pipeline applications efficiently. The programming model of the proposed architecture is compatible with the existing SMP operating systems. For the implementation of the pipeline-based parallelism, new programmer-friendly system calls are suggested to take advantage of the new software-pipeline datapath. The proposed architecture with four reduced instruction set computing cores is implemented on an field-programmable gate array development board for verification. An Advanced Video Coding/H.264 baseline profile video decoder that explores the pipeline parallelism with dynamic pipeline-stage partitioning is implemented on the target platform to justify the benefits of the proposed architecture. Experimental results show that the adoption of the proposed pipeline datapath architecture into existing application processors enables new potentials in exploring software parallelism.
Analysis of an SOC architecture for MPEG reconfigurable video coding framework
(2007)
Hsiao, Jer-Min
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
Due to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG Reconfigurable Video Coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this paper, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.
BAYESIAN DENSE MOTION FIELD ESTIMATION WITH LANDMARK CONSTRAINT
(2010)
Chin, Yi
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, a dense motion field estimation technique based on the Bayesian framework is proposed to estimate the true dense motion fields of video sequences. Previous stochastic techniques of dense motion field estimation adopts piecewise smooth motion model and use MAP estimation to find the motion field with joint minimization of motion compensation errors and maximization of motion smoothness. However, such random process does not guarantee to converge to the true motion field. In this paper, the motion of landmark points in the video sequence is introduced into the MAP estimation process to regularize the estimated motion field. Experimental results show that the proposed algorithm produces estimated motion fields which preserve piecewise smooth nature and are visually close to the true motion of the video sequences.
Content-Adaptive Packetization and Streaming of Wavelet Video over IP Networks
(2007)
Ho, Chien-Peng
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
This paper presents a framework of content-adaptive packetization scheme for streaming of 3D wavelet-based video content over lossy IP networks. The tradeoff between rate and distortion is controlled by jointly adapting scalable source coding rate and level of forward error correction (FEC) protection. A content dependent packetization mechanism with data-interleaving and Reed-Solomon protection for wavelet-based video codecs is proposed to provide unequal error protection. This paper also tries to answer an important question for scalable video streaming systems: given extra bandwidth, should one increase the level of channel protection for the most important packets, or transmit more scalable source data? Experimental results show that the proposed framework achieves good balance between quality of the received video and level of error protection under bandwidth-varying lossy IP networks. Copyright (c) 2007 C.-P. Ho and C.-J. Tsai.
DENSE TRUE MOTION FIELD COMPENSATION FOR VIDEO CODING
(2013-01-01)
Chin, Yi
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, a new motion compensation scheme based on dense true motion fields is investigated for video coding. The proposed technique is similar to the block-based decoder-side motion estimation method except that dense motion fields estimated from previously decoded frames are used for frame prediction. This paper demonstrates that even with compression distortions, an iterative dense true motion estimation technique can still produce good quality dense motion fields for video coding or frame-rate up-sampling applications. In particular, we have shown that when the new dense motion field compensation tool is integrated into the B-frame codec of H.264, one can achieve up to 8% overall BD bit-rate savings using standard MPEG test sequences.
Dynamic Pipeline-Partitioned Video Decoding on Symmetric Stream Multiprocessors
(2015)
Wu, Ming-Ju
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Chen, Yan-Ting
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture allows the processor cores to cooperate efficiently in a fine-grained software pipeline fashion. A traditional software pipelined video decoder has fixed pipeline-stage partitions. The AVC/H.264 video decoder investigated in this paper dynamically assigns different stages of the video macroblock (MB) decoding tasks to different processor cores in order to maintain load balance among the processor cores. The pipeline partitioning policy is based on the queue levels of the inter-stage buffers. Experimental results show that, on average, the proposed dynamic pipeline-partitioning video decoder is 34% faster compared to a wavefront-based parallel video decoder.
Dynamic Task Partition for Video Decoding on Heterogeneous Dual-Core Platforms
(2013-03-01)
Tsai, Chun-Jen
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Shen, Tsung-Fan
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Liao, Pei-Ching
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資訊工程學系
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Department of Computer Science
This article presents the design of a video decoder using dynamic task partition approach on a heterogeneous dual-core embedded platform. For such systems, static task partition between the two cores at design time is a typical approach for application development. In this article, we propose a runtime dynamic task partition model and implement an MPEG-4 Simple Profile video decoder using this approach on a TI OMAP 5912 platform. Comparing with a traditional mobile video decoder optimized for the same DSP core, the performance gain from dynamic task partition is 38.4% on average. More importantly, the gain is achieved with the design constraint that the implementation effort for the dynamic task partition decoder is about the same as the effort using design-time task partition model. Unlike common belief that the inter-processor communication overhead would be too high to justify intense cooperation between two heterogeneous cores, this paper shows that it is indeed beneficial to adopt dynamic task partition model on commercially available heterogeneous multi-core platforms.
Fast Host Service Interface Design for Embedded Java Application Processor
(2009)
Su, Kuan-Nian
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, we have proposed a fast inter-processor communication interface (IPC) for a dual-core Java application processor. The dual-core Java application processor is a SoC composed of a RISC core and a double-issued Java bytecode execution core. The proposed fast IPC mechanism provides Java system software a high-level way to invoke a host processor service routine from Java source code. The proposed IPC has much lower overhead than that of the standard Java Native Interface (JNI). Unlike other fast native call interface designed for VM interpreter, the proposed IPC mechanism is exclusively designed for the communication between two physical hardwired processor cores. Based on the experimental results, the proposed mechanism is very promising for embedded Java runtime environment.
Hardware-assisted Syntax Decoding Model for Software AVC/H.264 Decoders
(2009)
Wu, Ming-Ju
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Chen, Yi-Tseng
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, we have proposed an efficient hardware-assisted syntax decoding model for software-based video decoder. The proposed syntax decoding model is a generic model for different video codec standards. The syntax decoding process is divided into codec-dependent high-level syntax parser and generic entropy decoding engines. Currently, the design is implemented specifically for the support of AVC/H.264 standard (for both CAVLC and CABAC acceleration). Nevertheless, the design of the proposed syntax decoding model has the potential of becoming the design of a flexible bitstream parser, which is the most challenging problem in the MPEG Reconfigurable Video Coding (RVC) Framework A Virtex-5 FPGA development board is used to implement and verify the full hardware-software system (including the hardware entropy engines and the software syntax parser and macroblock data reconstruction modules extracted from JM12.2).
Hardwiring the OS Kernel into a Java Application Processor
(2017-01-01)
Tsai, Chun-Jen
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Lin, Cheng-Ju
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Chen, Cheng-Yang
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Lin, Yan-Hung
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Ji, Wei-Jhong
This paper presents the design and implementation of a hardwired OS kernel circuitry inside a Java application processor to provide the system services that are traditionally implemented in software. The hardwired system functions in the proposed SoC include the thread manager, the memory manager, and the I/O subsystem interface. There are many advantages in making the OS kernel a hardware component, such as a fast system boot time, highly efficient single-core multi-thread context-switching performance, and a better potential for supporting a complex multi-level memory subsystem. In addition, since the target application processor used in this paper is based on a Java processor, the system is not susceptible to the stack and pointer-based security attacks that are common to the register-based processors. Full-system performance evaluations on an FPGA show that the proposed system is very promising for deeply-embedded multi-thread applications.
JAIP-MP: A Four-Core Java Application Processor
(2015)
Tsai, Chun-Jen
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Wu, Tsung-Han
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Su, Hung-Cheng
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資訊工程學系
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Department of Computer Science
In this paper, we present the design of a four-core Java application processor, JAIP-MP. Each processor core in JAIP-MP is a hardwired Java core that supports dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method and object caching, Java exception handling, and temporal multithreading. For JAIP-MP, a global load-balancing task manager is used to evenly distribute Java threads among the local task queues of every processor cores. In addition, a data coherence controller is designed to enforce coherence across all data caches and to perform synchronization operations among Java threads of all processor cores. Since thread management and synchronization mechanisms are completely implemented in hardware, the single-core multi-tasking performance of JAIP-MP is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. For execution of multithreading applications, the speedup of a four-core JAIP-MP system can be up to 3.69 times faster than a single-core JAIP system, tested using the JemBench parallel benchmark programs.
JAIP-MP: A Four-Core Java Application Processor for Embedded Systems
(2016)
Tsai, Chun-Jen
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Wu, Tsung-Han
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Su, Hung-Cheng
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Chen, Cheng-Yang
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資訊工程學系
In this chapter, we present a four-core Java application processor, JAIP-MP. In addition to supporting multi-core coherent data accesses to shared memory, each processor core in JAIP-MP is a hardwired Java core that is capable of dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method/object caching, Java exception handling, preemptive multi-threading, and memory management. Most of the essential OS kernel functions are implemented in hardware. In particular, the preemptive multi-threading performance is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. Currently, single-cycle context switching with a time quantum as small as 20 mu s can be achieved by each core. More importantly, the Java language model itself makes it possible to maintain binary portability of application software regardless of the hardwired OS kernel component. In summary, JAIP-MP could be used to study the potential benefits of OS kernel implementation in hardware.
Low-Cost Class Caching Mechanism for Java SoC
(2010)
Hwang, Chien-Feng
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Su, Kuan-Nian
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, we have presented a low-cost Java class caching mechanism for Java processors. The design is integrated into a heterogeneous dual-core Java SoC that is targeted for embedded multimedia applications with GUI support. The design goal of the proposed caching mechanism is to improve the Java program execution performance without the complexity of a multi-way set associative cache. Since object-oriented Java programs are usually composed of many small classes, the proposed low-cost caching mechanism works fairly well for practical applications. The Java SoC is implemented and emulated on an Xilinx Virtex-4 device and the benchmark results show that the performance of the proposed dual-core Java SoC is faster than other popular software-based VMs for embedded systems.
Multiple adaptations and content-adaptive FEC using parameterized RD model for embedded wavelet video
(2007)
Yu, Ya-Huei
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Ho, Chien-Peng
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
Scalable video coding ( SVC) has been an active research topic for the past decade. In the past, most SVC technologies were based on a coarse-granularity scalable model which puts many scalability constraints on the encoded bitstreams. As a result, the application scenario of adapting a preencoded bitstream multiple times along the distribution chain has not been seriously investigated before. In this paper, a model-based multiple-adaptation framework based on a wavelet video codec, MC-EZBC, is proposed. The proposed technology allows multiple adaptations on both the video data and the content-adaptive FEC protection codes. For multiple adaptations of video data, rate-distortion information must be embedded within the video bitstream in order to allow rate-distortion optimized operations for each adaptation. Experimental results show that the proposed method reduces the amount of side information by more than 50% on average when compared to the existing technique. It also reduces the number of iterations required to perform the tier-2 entropy coding by more than 64% on average. In addition, due to the nondiscrete nature of the rate-distortion model, the proposed framework also enables multiple adaptations of content-adaptive FEC protection scheme for more flexible error-resilient transmission of bitstreams. Copyright (c) 2007 Ya-Huei Yu et al.
Perceptual-based distributed video coding
(2012-04-01)
Sun, Yu-Chen
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, we propose a perceptual-based distributed video coding (DVC) technique. Unlike traditional video codecs, DVC applies video prediction process at the decoder side using previously received frames. The predicted video frames (i.e., side information) contain prediction errors. The encoder then transmits error-correcting parity bits to the decoder to reconstruct the video frames from side information. However, channel codes based on i.i.d. noise models are not always efficient in correcting video prediction errors. In addition, some of the prediction errors do not cause perceptible visual distortions. From perceptual coding point of view, there is no need to correct such errors. This paper proposes a scheme for the decoder to perform perceptual quality analysis on the predicted side information. The decoder only requests parity bits to correct visually sensitive errors. More importantly, with the proposed technique, key frames can be encoded at higher rates while still maintaining consistent visual quality across the video sequence. As a result, even the objective PSNR measure of the decoded video sequence will increase too. Experimental results show that the proposed technique improves the R-D performance of a transform domain DVC codec both subjectively and objectively. Comparisons with a well-known DVC codec show that the proposed perceptual-based DVC coding scheme is very promising for distributed video coding framework. (C) 2012 Elsevier Inc. All rights reserved.
PRIORITIZED SIDE INFORMATION CORRECTION FOR DISTRIBUTED VIDEO CODING
(2009)
Sun, Yu-Chen
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Lian, Shiau-Yu
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
In this paper, a distributed video coding technique with prioritized channel coding of W-Z frames is presented. In the proposed framework, W-Z frame macroblocks are classified into different groups based on the estimated quality of the side information. The information is transmitted via uplink channel back to the encoder so that macroblocks with similar error statistics can be grouped tighter in same coding blocks for channel coding. With this approach, decoder can request more parity bits to correct macroblocks whose side information quality is worse and request less parity bits for macroblocks with smaller side information errors. Initial experimental results show that the proposed technique call improve the R-D performance of both pixel-domain and transform-domain DVC codecs considerably.