Browsing by Author "Tsai, Chung-Han"

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A Novel Readout Chip with Extendability for Multi-Channel EEG Measurement
(2013-01-01)
Chen, Yi-Chung
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Tsai, Chung-Han
;
Hsieh, Zong-Han
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
This paper proposes an extendable front-end readout chip (EFRC) for electroencephalography (EEG) measurements. An EFRC is developed for EEG measurement with features including low power consumption, a high signal-to-noise ratio, and highly efficient chip area usage. A chopper-stabilized differential difference amplifier (CHDDA) is used in the first stage to amplify signals and then during another adjustable amplification stage and filter are used to process biomedical signals. A 10-bit successive approximation register analog-to-digital converter (SAR-ADC) then links to the back-end for digital signal processing. In the last stage, shift-register pairs are used to transmit data to the next chip and receive data from the previous chip. The shift register design allows the number of channels to be extended. A TSMC 0.18 um CMOS process is used to design the EFRC and it operates with a 1.8 V supply voltage. The results shows that the total power consumption for the EFRC chip is approximately 80.268 uW and the chip area is approximately 944 x 863 um(2).
A Wireless Biomedical Sensor Network using IEEE802.15.4
(2009)
Tseng, Shao-Yen
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Tsai, Chung-Han
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Lai, Yu-Sheng
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Fang, Wai-Chi
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電子工程學系及電子研究所
The advancements of wireless body area networks (WBAN) and wireless personal area networks (WPAN) has led to a recent increase of viable applications in wireless medical and healthcare devices. Developing biomedical sensors such as electroencephalograph (EEG) and electrocardiogram (ECG) sensors often require numerous connecting wires which may introduce noise and increase patient discomfort In this paper we propose a system design and realization of a wireless EEG and ECG sensor network focusing on issues such as time synchronization, bandwidth, and power constraints constituent of WBANs. Our WSN comprises three transmitting nodes for a total of four EEG channels and an ECG channel. We solve problems such as data throughput requirements for EEG and ECG signal processing as well as time synchronization of received data at the base station. This paper keeps in consideration the possible implementation of our proposed system onto a system-on-chip (SOC) by putting focus on the chip size and low power consumption of the analog-front-end system.